公开(公告)号：US20240186237A1

公开(公告)日：2024-06-06

申请号：US18353577

申请日：2023-07-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori TSUTSUMI

IPC: H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A memory device includes at least one alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through each layer within the at least one alternating stack, memory opening fill structures located in the memory openings and containing a respective vertical semiconductor channel and a respective vertical stack of memory elements, and an electrically conductive side-contact via structure vertically extending through each layer within the at least one alternating stack and contacting a sidewall of one of the electrically conductive layers.

公开(公告)号：US20240185900A1

公开(公告)日：2024-06-06

申请号：US18353294

申请日：2023-07-17

Applicant: SanDisk Technologies LLC

Inventor： TIANYU TANG

IPC: G11C7/14 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/14 ,  G11C7/1096 ,  G11C7/222

Abstract: Systems and methods disclosed herein provide for fast write training that be performed to identify an optimal reference voltage for distinguishing between logic levels of an input signal. An example of the systems and methods disclosed herein include receiving a clock signal at an input-output pad of a receiving device and detecting a voltage level of the clock signal based on a duty cycle and voltage swing of the clock signal. A voltage generator circuit is trained to generate a calibrated reference voltage according to the detected voltage level, and the calibrated reference voltage is supplied to an input receiver of the receiving device from the voltage generator circuit.

公开(公告)号：US20240184468A1

公开(公告)日：2024-06-06

申请号：US18224477

申请日：2023-07-20

Applicant: SanDisk Technologies LLC

Inventor： Wei Cao ,  Xiang Yang

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to identify at least one grouping of the memory cells to be programmed with a multi-pass programming operation. The control means is also configured to program the at least one grouping of the memory cells using the multi-pass programming operation. The control means is additionally configured to program the memory cells other than the at least one grouping of the memory cells in a full sequence programming operation.

公开(公告)号：US12004357B2

公开(公告)日：2024-06-04

申请号：US17654768

申请日：2022-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lei Wan ,  Jordan Katine ,  Tsai-Wei Wu ,  Chu-Chen Fu

IPC: G11C11/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/10 ,  H10N50/01 ,  H10N50/80

Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.

公开(公告)号：US12004348B2

公开(公告)日：2024-06-04

申请号：US17347810

申请日：2021-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuki Mizutani ,  Fumiaki Toyama ,  Masaaki Higashitani

IPC: H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A bonded assembly includes a memory die that is bonded to a logic die. The memory die includes a three-dimensional memory array located on a memory-side substrate, memory-side dielectric material layers located on the three-dimensional memory array and embedding memory-side metal interconnect structures and memory-side bonding pads, a backside peripheral circuit located on a backside surface of the memory-side substrate, and backside dielectric material layers located on a backside of the memory-side substrate and embedding backside metal interconnect structures. The logic die includes a logic-side peripheral circuit located on a logic-side substrate, and logic-side dielectric material layers located between the logic-side substrate and the memory die and embedding logic-side metal interconnect structures and logic-side bonding pads that are bonded to a respective one of the memory-side bonding pads.

公开(公告)号：US20240179916A1

公开(公告)日：2024-05-30

申请号：US18221711

申请日：2023-07-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno ,  Kota Funayama

IPC: H10B43/35 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  H01L23/5226 ,  H01L23/5283 ,  H10B43/10 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers having stepped surfaces in a contact region, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, at least one retro-stepped dielectric material portion overlying the alternating stack, finned dielectric pillar structures vertically extending through the alternating stack in the contact region, support pillar structures, and layer contact via structures vertically extending through the at least one retro-stepped dielectric material portion. Each of the layer contact via structures contacts a respective one of the electrically conductive layers and a respective one of the finned dielectric pillar structures.

公开(公告)号：US20240179904A1

公开(公告)日：2024-05-30

申请号：US18240560

申请日：2023-08-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tomohiro KUBO ,  Takayuki MAEKURA

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A method includes forming an in-process alternating stack of insulating layers and sacrificial material layers, forming a meandering dielectric isolation structure through the in-process alternating stack, forming memory stack structures through the alternating stack, where each of the memory stack structures includes a respective vertical stack of memory elements and a vertical semiconductor channel, forming sacrificial via fill structures on the respective sacrificial material layers, replacing first portions of the sacrificial material layers with electrically conductive layers, and forming layer contact via structures contacting a respective one of the electrically conductive layers by replacing at least the sacrificial via fill structures with a conductive material portion.

公开(公告)号：US20240179897A1

公开(公告)日：2024-05-30

申请号：US18351205

申请日：2023-07-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Fei ZHOU

IPC: H10B41/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer, a continuous charge storage material layer vertically extending through a plurality of the electrically conductive layers, a vertical stack of discrete charge storage elements located at levels of the electrically conductive layers and contacting a respective surface segment of an outer sidewall of the continuous charge storage material layer, and a vertical stack of discrete blocking dielectric material portions containing silicon atoms and oxygen atoms and located at the levels of the electrically conductive layers and vertically spaced apart from each other.

公开(公告)号：US20240172431A1

公开(公告)日：2024-05-23

申请号：US18425996

申请日：2024-01-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Johann ALSMEIER ,  Lito De La RAMA ,  Masaaki HIGASHITANI ,  Koichi MATSUNO ,  Marika GUNJI-YONEOKA ,  Makoto KOTO ,  Hisakazu OTOI ,  Masanori TSUTSUMI

IPC: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L29/06 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L29/0653 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a plurality of source layers, where the electrically conductive layers include word lines and source-side select gate electrodes which are located between the plurality of source layers and the word lines in a vertical direction, groups of memory openings vertically extending through the alternating stack, and groups of memory opening fill structures located in the groups of memory openings. The plurality of source layers are laterally spaced apart and electrically isolated from each other, and each respective one of the plurality of source layers contacts at least one respective group of the groups of memory opening fill structures.

公开(公告)号：US11984395B2

公开(公告)日：2024-05-14

申请号：US17479637

申请日：2021-09-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  Fei Zhou

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.