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182 条记录 (耗时 0.037 秒)

    Field effect transistor
    61.
    发明授权
    Field effect transistor 失效
    场效应晶体管

    公开(公告)号：US5677573A

    公开(公告)日：1997-10-14

    申请号：US743502

    申请日：1996-11-04

    申请人： Kirk Prall ,  Pai-Hung Pan ,  Sujit Sharan

    发明人： Kirk Prall ,  Pai-Hung Pan ,  Sujit Sharan

    IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/08 ,  H01L29/43

    CPC分类号： H01L29/66628 ,  H01L21/2257 ,  H01L29/0847 ,  Y10S438/969

    摘要： A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, i) produce doped monocrystalline silicon extending outwardly from the substrate surface, and ii) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces. A field effect transistor is also claimed.

    摘要翻译： 一种形成相对于单晶硅衬底的场效晶体管的方法，其中晶体管具有升高的源极和升高的漏极，包括：a）在单晶硅衬底上提供晶体管栅极，栅极被封装在电绝缘材料中; b）提供与晶体管栅极相邻的外部暴露的单晶硅衬底表面; c）清洁外部暴露的基底表面以从其中除去氧化物和杂质; d）在快速热化学气相沉积反应器内部，并且在清洁步骤之后，在与晶体管栅极相邻的清洁的衬底表面上化学气相沉积导电掺杂的非多晶硅层，非多晶硅层具有外表面，衬底 不会在清洗时间和化学气相沉积之间暴露于氧化或污染条件; 以及e）在化学气相沉积之后，将所述掺杂的非多晶硅层暴露于高温退火条件，所述高温退火条件有效地，i）产生从所述衬底表面向外延伸的掺杂单晶硅，以及ii）产生从所述外表面向内延伸的掺杂多晶硅 ; 掺杂的单晶硅和掺杂的多晶硅在衬底表面的高度位移的界面处接合。 还要求一种场效应晶体管。

    Sacrificial CVD germanium layer for formation of high aspect ratio submicron VLSI contacts
    62.
    发明授权
    Sacrificial CVD germanium layer for formation of high aspect ratio submicron VLSI contacts 失效
    用于形成高纵横比亚微米VLSI触点的牺牲CVD锗层

    公开(公告)号：US5644166A

    公开(公告)日：1997-07-01

    申请号：US503385

    申请日：1995-07-17

    申请人： Jeffrey Honeycutt ,  Sujit Sharan

    发明人： Jeffrey Honeycutt ,  Sujit Sharan

    IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L23/48

    CPC分类号： H01L21/76858 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002

    摘要： A high aspect ratio submicron VLSI contact and corresponding method of manufacture is disclosed. The contact is formed through an insulative layer, such as silicon dioxide, to an underlying active region on a substrate of silicon wafer. The contact comprises a layer of titanium germanosilicide at the bottom of the contact opening, and a layer of titanium germanide at the sides of the contact opening, with an overlying layer of titanium nitride. The contact is metallized, preferably using tungsten or aluminum. The disclosed method of manufacturing the contact comprises first etching the contact opening, then exposing the bottom of the contact opening to germane gas to clean native silicon dioxide from the bottom of the contact opening. A 50 Angstrom layer of germanium is then deposited over the contact opening. A layer of titanium is then deposited over the germanium layer in the contact opening. The deposition of titanium is preferably accomplished using a collimator having an aspect ratio lower than about 2.5:1. After annealing in a nitrogen atmosphere, the contact is metallized with tungsten or aluminum. The anneal step can be conducted at a temperature of around 600.degree. C. Less titanium may be used than with conventional processes, allowing a higher aspect ratio of the contact opening as well as the use of the collimator having a lower than conventional aspect ratio.

    摘要翻译： 公开了高纵横比亚微米VLSI接触和相应的制造方法。 该触点通过诸如二氧化硅的绝缘层形成到硅晶片的衬底上的下面的有源区上。 接触包括在接触开口底部的锗硅酸锗层和在接触开口侧的锗锗锗层，并且覆盖有氮化钛层。 接触金属化，优选使用钨或铝。 所公开的制造接触的方法包括首先蚀刻接触开口，然后将接触开口的底部暴露于锗烷气体以从接触开口的底部清洁天然二氧化硅。 然后在接触开口上沉积50埃的锗层。 然后在接触开口中的锗层上沉积一层钛。 钛的沉积优选使用纵横比低于约2.5:1的准直器来实现。 在氮气气氛中退火后，接触件用钨或铝金属化。 退火步骤可以在大约600℃的温度下进行。与常规方法相比，可以使用较少的钛，允许接触开口的更高的纵横比以及具有低于常规纵横比的准直器的使用。

    SELF ALIGNED SORT PROBE CARD FOR SI BRIDGE WAFER
    63.
    发明申请
    SELF ALIGNED SORT PROBE CARD FOR SI BRIDGE WAFER 审中-公开

    公开(公告)号：US20190271721A1

    公开(公告)日：2019-09-05

    申请号：US16322430

    申请日：2016-09-30

    申请人： Dae-Woo KIM ,  Sujit SHARAN

    发明人： Dae-Woo KIM ,  Sujit SHARAN

    IPC分类号： G01R1/073 ,  G01R31/26 ,  G01R31/28

    摘要： Apparatus and methods for adjusting probes of a integrated circuit tester are provided. In an examples, an apparatus can include an array of probes having a nominal pitch, a space transformer configured to provide electrical connections from a plurality of terminals of the space transformer to the plurality of probes, wherein a second nominal pitch of the plurality of terminals is different than the nominal pitch of the probes, and a thermal device configured to adjust a nominal spacing of the array of probes using heat transfer.

    METHODS OF FORMING HIGHLY ORIENTED DIAMOND FILMS AND STRUCTURES FORMED THEREBY
    67.
    发明申请
    METHODS OF FORMING HIGHLY ORIENTED DIAMOND FILMS AND STRUCTURES FORMED THEREBY 审中-公开
    形成高精度金刚石薄膜的方法及其形成的结构

    公开(公告)号：US20080237718A1

    公开(公告)日：2008-10-02

    申请号：US11694626

    申请日：2007-03-30

    申请人： Vladimir Noveski ,  Sujit Sharan ,  Aleksandar Aleksov

    发明人： Vladimir Noveski ,  Sujit Sharan ,  Aleksandar Aleksov

    IPC分类号： H01L27/12 ,  H01L21/8238

    CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L21/84

    摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a first HOD layer on a first side of a first silicon substrate, forming a CMOS region on a second side of the silicon substrate, forming amorphous silicon on the CMOS region, recrystallizing the amorphous silicon to form a first single crystal silicon layer, and forming a second HOD layer on the first single crystal silicon layer.

    摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括在第一硅衬底的第一侧上形成第一HOD层，在硅衬底的第二侧上形成CMOS区域，在CMOS区域上形成非晶硅，使非晶硅重结晶以形成第一单晶 硅层，并在第一单晶硅层上形成第二HOD层。

    Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks
    69.
    发明授权
    Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks 有权
    形成和利用抗反射材料层的半导体加工方法，以及形成晶体管栅叠层的方法

    公开(公告)号：US07151054B2

    公开(公告)日：2006-12-19

    申请号：US10805557

    申请日：2004-03-19

    申请人： Gurtej S. Sandhu ,  Sujit Sharan

    发明人： Gurtej S. Sandhu ,  Sujit Sharan

    IPC分类号： H01L21/4763

    CPC分类号： G03F7/091 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/28123 ,  H01L21/3145

    摘要： In one aspect, the invention includes a semiconductor processing method comprising exposing silicon, nitrogen and oxygen in gaseous form to a high density plasma during deposition of a silicon, nitrogen and oxygen containing solid layer over a substrate.In another aspect, the invention includes a gate stack forming method, comprising: a) forming a polysilicon layer over a substrate; b) forming a metal silicide layer over the polysilicon layer; c) depositing an antireflective material layer over the metal silicide utilizing a high density plasma; d) forming a layer of photoresist over the antireflective material layer; e) photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist; and f) transferring a pattern from the patterned masking layer to the antireflective material layer, metal silicide layer and is polysilicon layer to pattern the antireflective material layer, metal silicide layer and polysilicon layer into a gate stack.

    摘要翻译： 在一个方面，本发明包括一种半导体处理方法，包括在衬底上沉积含硅，含氮和氧的固体层时，将硅，氮和氧气体暴露于高密度等离子体。 在另一方面，本发明包括一种栅堆叠形成方法，包括：a）在衬底上形成多晶硅层; b）在所述多晶硅层上形成金属硅化物层; c）利用高密度等离子体在金属硅化物上沉积防反射材料层; d）在抗反射材料层上形成一层光致抗蚀剂; e）光刻地图案化所述光致抗蚀剂层以从所述光致抗蚀剂层形成图案化掩模层; 以及f）将图案从图案化掩模层转移到抗反射材料层，金属硅化物层，并且是将抗反射材料层，金属硅化物层和多晶硅层图案化成栅叠层的多晶硅层。

    Metal silicide adhesion layer for contact structures
    70.
    发明申请
    Metal silicide adhesion layer for contact structures 审中-公开
    用于接触结构的金属硅化物粘合层

    公开(公告)号：US20060202283A1

    公开(公告)日：2006-09-14

    申请号：US11418159

    申请日：2006-05-03

    申请人： Ammar Deraa ,  Sujit Sharan ,  Paul Castrovillo

    发明人： Ammar Deraa ,  Sujit Sharan ,  Paul Castrovillo

    IPC分类号： H01L29/76

    CPC分类号： H01L21/76846 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A high aspect ratio contact structure using a metal silicide adhesion layer that is interposed between titanium and titanium nitride (TiN) to promote adhesion of TiN to Ti. The metal silicide adhesion layer created from silicon doped CVD Ti can be deposited over the unreacted Ti after the silicidation reaction or deposited directly on the silicon substrate in place of CVD Ti. The contact structure further includes contact fill that is comprised of TiCl4 based TiN, which affords improved step coverage in the contact structure.

    摘要翻译： 使用介于钛和氮化钛（TiN）之间的金属硅化物粘附层的高纵横比接触结构以促进TiN与Ti的粘附。 由硅掺杂的CVD Ti产生的金属硅化物粘附层可以在硅化反应之后沉积在未反应的Ti上，或者直接沉积在硅衬底上而不是CVD Ti。 接触结构还包括由基于TiCl 4的TiN组成的接触填充，其提供接触结构中改进的台阶覆盖。