公开(公告)号：US08823141B2

公开(公告)日：2014-09-02

申请号：US13255648

申请日：2010-03-08

申请人： Tomoyuki Takada ,  Masahiko Hata ,  Sadanori Yamanaka

发明人： Tomoyuki Takada ,  Masahiko Hata ,  Sadanori Yamanaka

IPC分类号： H01L29/20 ,  H01L21/02

CPC分类号： H01L21/0237 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02642 ,  H01L29/107 ,  H01L29/73 ,  H01L29/7371 ,  H01L29/772

摘要： The semiconductor wafer includes: a base wafer; and an inhibition layer that is disposed on the base wafer as one piece or to be separate portions from each other, and inhibits growth of a crystal of a compound semiconductor, where the inhibition layer has a plurality of first opening regions that have a plurality of openings penetrating the inhibition layer and leading to the base wafer, each of the plurality of first opening regions includes therein a plurality of first openings disposed in the same arrangement, some of the plurality of first openings are first element forming openings each provided with a first compound semiconductor on which an electronic element is to be formed, and the other of the plurality of first openings are first dummy openings in which no electronic element is to be formed.

摘要翻译： 半导体晶片包括：基底晶片; 以及抑制层，其一体地设置在所述基底晶片上或者彼此分离，并且抑制化合物半导体的晶体的生长，其中所述抑制层具有多个第一开口区域，所述第一开口区域具有多个 穿过所述抑制层并通向所述基底晶片的开口，所述多个第一开口区域中的每一个在其中包括设置在相同布置中的多个第一开口，所述多个第一开口中的一些是第一元件形成开口，每个元件形成开口设置有第一 其上形成有电子元件的复合半导体，并且多个第一开口中的另一个是其中不形成电子元件的第一虚拟开口。

公开(公告)号：US08779471B2

公开(公告)日：2014-07-15

申请号：US13413216

申请日：2012-03-06

申请人： Masahiko Hata ,  Hisashi Yamada ,  Noboru Fukuhara ,  Shinichi Takagi ,  Mitsuru Takenaka ,  Masafumi Yokoyama ,  Tetsuji Yasuda ,  Yuji Urabe ,  Noriyuki Miyata ,  Taro Itatani ,  Hiroyuki Ishii

发明人： Masahiko Hata ,  Hisashi Yamada ,  Noboru Fukuhara ,  Shinichi Takagi ,  Mitsuru Takenaka ,  Masafumi Yokoyama ,  Tetsuji Yasuda ,  Yuji Urabe ,  Noriyuki Miyata ,  Taro Itatani ,  Hiroyuki Ishii

IPC分类号： H01L29/66

CPC分类号： H01L29/7786 ,  H01L21/26553 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66318 ,  H01L29/66522

摘要： Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0

摘要翻译： 提供了一种场效应晶体管，其包括栅极绝缘层，与栅极绝缘层接触的第一半导体晶体层和第二半导体晶体层与第一半导体晶体层的晶格匹配或伪晶格匹配。 这里，栅绝缘层，第一半导体晶体层和第二半导体晶体层按栅极绝缘层，第一半导体晶体层和第二半导体晶体层的顺序排列，第一半导体晶体层被制成 的In x Ga 1-x As y 1 P 1-y 1（0

公开(公告)号：US08716836B2

公开(公告)日：2014-05-06

申请号：US12811011

申请日：2008-12-26

申请人： Tomoyuki Takada ,  Sadanori Yamanaka ,  Masahiko Hata ,  Taketsugu Yamamoto ,  Kazumi Wada

发明人： Tomoyuki Takada ,  Sadanori Yamanaka ,  Masahiko Hata ,  Taketsugu Yamamoto ,  Kazumi Wada

IPC分类号： H01L21/331 ,  H01L29/737

CPC分类号： H01L21/8258 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02546 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/8252 ,  H01L29/66318

摘要： A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; and a functional layer that is crystal-grown on the Ge layer. The Ge layer may be formed by annealing with a temperature and duration that enables movement of crystal defects, and the annealing is repeated a plurality of times.

摘要翻译： 实现了具有良好热释放特性的廉价Si晶片的高质量GaAs型晶体薄膜。 提供了包括Si晶片的半导体晶片; 所述抑制层形成在所述晶片上并且抑制晶体生长，所述抑制层包括覆盖所述晶片的一部分的覆盖区域和不覆盖所述覆盖区域内的所述晶片的一部分的开放区域; 在开放区域晶体生长的Ge层; 以及在Ge层上晶体生长的功能层。 Ge层可以通过使得能够移动晶体缺陷的温度和持续时间退火而形成，并且退火重复多次。

公开(公告)号：US08633496B2

公开(公告)日：2014-01-21

申请号：US13310451

申请日：2011-12-02

申请人： Masahiko Hata ,  Sadanori Yamanaka ,  Tomoyuki Takada

发明人： Masahiko Hata ,  Sadanori Yamanaka ,  Tomoyuki Takada

IPC分类号： H01L27/15

CPC分类号： H01L27/1446 ,  H01L21/02439 ,  H01L21/02441 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02524 ,  H01L27/14601 ,  H01L27/15 ,  H01L27/156 ,  H01L29/161 ,  H01L29/267 ,  H01L29/7371 ,  H01S5/021

摘要： Provided is an optical device including a base wafer containing silicon, a plurality of seed crystals disposed on the base wafer, and a plurality of Group 3-5 compound semiconductors lattice-matching or pseudo lattice-matching the plurality of seed crystals. At least one of the Group 3-5 compound semiconductors has a photoelectric semiconductor formed therein, the photoelectric semiconductor including a light emitting semiconductor that emits light in response to a driving current supplied thereto or a light receiving semiconductor that generates a photocurrent in response to light applied thereto, and at least one of the plurality of Group 3-5 compound semiconductors other than the Group 3-5 compound semiconductor having the photoelectric semiconductor has a heterojunction transistor formed therein.

摘要翻译： 提供了一种光学器件，其包括含有硅的基底晶片，设置在基底晶片上的多个晶种，以及多个晶格匹配或伪晶格匹配多个晶种的3-5族化合物半导体。 第3-5组化合物半导体中的至少一个具有形成在其中的光电半导体，该光电半导体包括响应于提供的驱动电流而发光的发光半导体或响应于光产生光电流的光接收半导体 并且除了具有光电半导体的组3-5化合物半导体之外的多个3-5族化合物半导体中的至少一个具有形成在其中的异质结晶体管。

公开(公告)号：US08507952B2

公开(公告)日：2013-08-13

申请号：US13495746

申请日：2012-06-13

申请人： Sadanori Yamanaka ,  Tomoyuki Takada ,  Masahiko Hata

发明人： Sadanori Yamanaka ,  Tomoyuki Takada ,  Masahiko Hata

IPC分类号： H01L21/02

CPC分类号： H01L21/02639 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02546

摘要： To improve the flatness of the surface and improve the reliability of a semiconductor device when expitaxially growing semiconductor crystal layers of different types on a single silicon wafer, provided is a semiconductor wafer which includes: a base wafer having a silicon crystal in the surface thereof, the silicon crystal having a first dent and a second dent; a first Group IVB semiconductor crystal located in the first dent and exposed; a second Group IVB semiconductor crystal located in the second dent; and a Group III-V compound semiconductor crystal located above the second Group IVB semiconductor crystal in the second dent and exposed.

摘要翻译： 为了提高表面的平坦度，提高在单晶硅晶片上外延生长不同种类的半导体晶体层时的半导体器件的可靠性，提供了一种半导体晶片，其包括：在其表面具有硅晶体的基底晶片， 所述硅晶体具有第一凹陷和第二凹陷; 第一组IVB半导体晶体位于第一凹陷中并暴露; 位于第二凹陷中的第二组IVB半导体晶体; 以及位于第二凹陷中的第二IVB族半导体晶体上方并暴露的III-V族化合物半导体晶体。

公开(公告)号：US08350292B2

公开(公告)日：2013-01-08

申请号：US12527116

申请日：2008-02-07

申请人： Naohiro Nishikawa ,  Hiroyuki Sazawa ,  Masahiko Hata

发明人： Naohiro Nishikawa ,  Hiroyuki Sazawa ,  Masahiko Hata

IPC分类号： H01L29/66

CPC分类号： H01L29/66462 ,  H01L29/2003 ,  H01L29/7783

摘要： The present invention provides a gallium nitride type epitaxial crystal, a method for producing the crystal, and a field effect transistor using the crystal. The gallium nitride type epitaxial crystal comprises a base substrate and the following (a) to (e), wherein a connection layer comprising a gallium nitride type crystal is arranged in an opening of the non-gallium nitride type insulating layer to electrically connect the first buffer layer and the p-conductive type semiconductor crystal layer. (a) a gate layer, (b) a high purity first buffer layer containing a channel layer contacting an interface on the base substrate side of the gate layer, (c) a second buffer layer arranged on the base substrate side of the first buffer layer, (d) a non-gallium nitride type insulating layer arranged on the base substrate side of the second buffer layer, and having the opening at a part thereof, and (e) a p-conductive type semiconductor crystal layer arranged on the base substrate side of the insulating layer.

摘要翻译： 本发明提供一种氮化镓型外延晶体，该晶体的制造方法以及使用该晶体的场效应晶体管。 氮化镓型外延晶体包括基底和以下（a）至（e），其中包括氮化镓型晶体的连接层被布置在非氮化镓型绝缘层的开口中，以将第一 缓冲层和p导电型半导体晶体层。 （a）栅极层，（b）高纯度第一缓冲层，其含有与栅极层的基底侧上的界面接触的沟道层，（c）第二缓冲层，其设置在第一缓冲层的基底侧 层，（d）配置在第二缓冲层的基板侧的非氮化镓系绝缘层，其一部分具有开口部，（e）配置在基板上的p导电型半导体晶体层 绝缘层的衬底侧。

公开(公告)号：US08173094B2

公开(公告)日：2012-05-08

申请号：US12159066

申请日：2006-12-26

申请人： Toshiharu Yamabayashi ,  Masahiko Hata

发明人： Toshiharu Yamabayashi ,  Masahiko Hata

IPC分类号： C01B33/02 ,  C01F3/00 ,  C01F7/48 ,  C01G15/00

CPC分类号： C01B33/033 ,  H01L31/182 ,  Y02E10/546 ,  Y02P70/521

摘要： The present invention provides a method for producing polycrystalline silicon. The method for producing polycrystalline silicon comprises the steps of (A), (B), and (C), (A) reducing a chlorosilane represented by the formula (1) with a metal at a temperature T1 to obtain a silicon compound; SiHnCl4-n  (1)  wherein n is an integer of 0 to 3, (B) transferring the silicon compound to a zone having a temperature T2, wherein T1>T2; and (C) depositing polycrystalline silicon in the zone having a temperature T2, wherein the temperature T1 is not less than 1.29 times of a melting point (Kelvin unit) of the metal, and the temperature T2 is higher than a sublimation point or boiling point of the chloride of the metal.

摘要翻译： 本发明提供一种多晶硅的制造方法。 制造多晶硅的方法包括以下步骤：（A），（B）和（C），（A）在温度T1下用金属还原由式（1）表示的氯代硅烷，得到硅化合物; SiHnCl4-n（1）其中n为0-3的整数，（B）将硅化合物转移到具有温度T2的区域，其中T1> T2; 和（C）在具有温度T2的区域中沉积多晶硅，其中温度T1不小于金属的熔点（开尔文单位）的1.29倍，并且温度T2高于升华点或沸点 的金属氯化物。

公开(公告)号：US08150647B2

公开(公告)日：2012-04-03

申请号：US12712172

申请日：2010-02-24

申请人： Masahiko Hata

发明人： Masahiko Hata

IPC分类号： G01R27/28

CPC分类号： G01R31/31721 ,  G01R31/3016

摘要： An electric device includes a plurality of circuits that operate in synchronization with a clock signal, a plurality of flip-flops each of which acquires a data value of a signal from a corresponding one of the plurality of circuits in synchronization with the clock signal and stores the acquired data value therein until receiving a next clock signal, where each flip-flop enters into a clock-disabled state, when receiving a signal at a disable terminal thereof, in which the acquired data value continues to be stored in the flip-flop, a timing controller that outputs a hold signal to the disable terminal of each flip-flop at a timing at which a corresponding circuit is desired to be diagnosed, and a plurality of diagnosis lines that are respectively provided in correspondence with the plurality of flip-flops, each diagnosis line outputting as diagnosis data a data value stored in a corresponding flip-flop.

摘要翻译： 电气设备包括与时钟信号同步操作的多个电路，多个触发器，每个触发器与时钟信号同步地从多个电路中的一个电路获取信号的数据值，并存储 其中所获取的数据值在接收到其中每个触发器进入时钟禁止状态的下一个时钟信号，当在其禁用端接收信号时，其中所获取的数据值继续存储在触发器 定时控制器，其在期望相应电路被诊断的定时将保持信号输出到每个触发器的禁止端子;以及多个诊断线，分别与多个触发器相对应地设置， 每个诊断线作为诊断数据输出存储在相应的触发器中的数据值。

公开(公告)号：US20110186911A1

公开(公告)日：2011-08-04

申请号：US13122107

申请日：2009-10-01

申请人： Masahiko Hata

发明人： Masahiko Hata

IPC分类号： H01L29/22 ,  H01L29/12 ,  H01L21/20

CPC分类号： H01L21/8258 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/02551 ,  H01L21/02645 ,  H01L21/02647 ,  H01L21/8252 ,  H01L27/1203 ,  H01L29/66742 ,  H01L29/7786 ,  H01L29/78681 ,  H01L29/812

摘要： There is provided a semiconductor wafer including a base wafer, an insulating layer, and a Si crystal layer in the stated order. Here, the semiconductor wafer includes a seed crystal disposed on the Si crystal layer where the seed crystal has been subjected to annealing, and a compound semiconductor that has a lattice match or a pseudo lattice match with the seed crystal. There is provided an electronic device including a substrate, an insulating layer disposed on the substrate, a Si crystal layer disposed on the insulating layer, a seed crystal disposed on the Si crystal layer where the seed crystal has been subjected to annealing, a compound semiconductor that has a lattice match or a pseudo lattice match with the seed crystal, and a semiconductor device formed using the compound semiconductor.

摘要翻译： 提供了以所述顺序包括基底晶片，绝缘层和Si晶体层的半导体晶片。 这里，半导体晶片包括配置在已经进行退火晶种的Si晶体层上的晶种和具有与晶种匹配的晶格匹配或伪晶格的化合物半导体。 提供了一种电子设备，包括基板，设置在基板上的绝缘层，设置在绝缘层上的Si晶体层，设置在已经进行晶种退火的Si晶体层上的晶种，化合物半导体 其具有晶种匹配或与晶种的伪晶格匹配，以及使用该化合物半导体形成的半导体器件。

公开(公告)号：US07951685B2

公开(公告)日：2011-05-31

申请号：US12310984

申请日：2007-09-14

申请人： Hiroyuki Sazawa ,  Naohiro Nishikawa ,  Masahiko Hata

发明人： Hiroyuki Sazawa ,  Naohiro Nishikawa ,  Masahiko Hata

IPC分类号： H01L21/76

CPC分类号： H01L29/66462 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/31608 ,  H01L21/31616 ,  H01L21/31645 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.

摘要翻译： 本发明提供一种具有电介质膜的氮化镓半导体外延晶体基板的制造方法，所述电介质膜具有低栅极泄漏电流和可忽略的低栅极滞后，漏极滞后和电流塌陷特性。 半导体外延晶体基板的制造方法是制造半导体外延晶体基板的方法，其中，作为钝化膜或栅极绝缘体的非晶形式的氮化物电介质材料或氧化物电介质材料的介电层设置在 通过金属有机化学气相沉积生长的氮化物半导体晶体层的表面。 在该方法中，在外延生长室中生长氮化物半导体晶体层之后，在外延生长室中的氮化物半导体晶体层上生长电介质层。