公开(公告)号：US06943439B2

公开(公告)日：2005-09-13

申请号：US10116204

申请日：2002-04-04

Applicant: Chien-Ping Huang ,  Han-Ping Pu ,  Chih-Chin Liao

Inventor： Chien-Ping Huang ,  Han-Ping Pu ,  Chih-Chin Liao

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/544 ,  H05K1/02 ,  H05K3/24 ,  H05K3/28 ,  H05K3/34 ,  H01L23/02 ,  H01L23/48 ,  H01L23/495 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/85 ,  H01L21/4846 ,  H01L22/34 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/48 ,  H01L2224/8501 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H05K1/0269 ,  H05K3/242 ,  H05K3/28 ,  H05K3/3489 ,  H05K2201/09781 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A substrate and a fabrication method thereof are proposed, with at least a check point being formed on the substrate. Prior to wire bonding and/or molding processes, cleanness of the substrate (cleaned by plasma) is determined according to color variation of the check point, so as to allow only cleaned and contamination-free substrates to be subsequently formed with bonding wires and encapsulants thereon. Thereby, qualities of wire-bonded electrical connection and encapsulant adhesion for the substrate can be assured, which helps prevent the occurrence of delamination between the encapsulant and the substrate. Moreover, the check point formed on the substrate is made during general substrate fabrication by using current equipment and technique, and in a manner as not to interfere with trace routability on the substrate; thereby, costs and complexity of substrate fabrication would not undesirably increased.

Abstract translation: 提出了一种基板及其制造方法，至少在基板上形成检查点。 在引线接合和/或模制工艺之前，根据检查点的颜色变化确定基材的清洁度（通过等离子体清洁），以便仅使用清洁和无污染的基材随后用接合线和密封剂形成 上。 因此，可以确保线接合电连接的质量和用于衬底的密封剂附着性，这有助于防止密封剂和衬底之间的分层的发生。 此外，通过使用当前的设备和技术，在通常的基板制造中形成的检查点，并且以不干扰基板上的迹线布线性的方式进行; 因此，衬底制造的成本和复杂性将不会不期望地增加。

公开(公告)号：US20050148117A1

公开(公告)日：2005-07-07

申请号：US11051172

申请日：2005-02-03

Applicant: Chien-Ping Huang

Inventor： Chien-Ping Huang

IPC: H01L21/56 ,  H01L21/82 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L23/495 ,  H01L23/498 ,  H01L23/52 ,  H01L27/10 ,  H01L29/40 ,  H01L29/739 ,  H01L31/0203

CPC classification number: H01L23/13 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/49 ,  H01L31/0203 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2924/15311 ,  H04N5/2257 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A flash-preventing window ball grid array semiconductor package, a method for fabricating the same, and a chip carrier used in the semiconductor package are provided. The chip carrier has a through hole and has a surface formed with a plurality of wire-bonding portions, ball-bonding portions and intended-exposing regions. A chip is mounted over the through hole and electrically connected to the wire-bonding portions by a plurality of bonding wires penetrating through the through hole. An encapsulation body encapsulates the chip and bonding wires. The intended-exposing regions serve as a narrow runner which is filled with an encapsulating material forming the encapsulation body, making the encapsulating material not flash over the ball-bonding portions. This allows a plurality of solder balls to be well bonded to the ball-bonding portions, thereby assuring the quality of electrical connection and the surface planarity of the semiconductor package.

Abstract translation: 提供防闪光窗球栅阵列半导体封装，其制造方法以及半导体封装中使用的芯片载体。 芯片载体具有通孔，并且具有形成有多个引线接合部分，滚珠接合部分和预期曝光区域的表面。 芯片安装在通孔上方，并通过贯穿通孔的多根接合线电连接到引线接合部分。 封装体封装芯片和接合线。 预期曝光区域用作填充有形成封装体的封装材料的窄流道，使得封装材料不会在滚珠焊接部分上闪动。 这允许多个焊球与滚珠焊接部分良好地结合，从而确保电连接的质量和半导体封装的表面平面度。

公开(公告)号：US20050139946A1

公开(公告)日：2005-06-30

申请号：US10959786

申请日：2004-10-05

Applicant: Chia-Yu Hung ,  Chien-Ping Huang ,  Ke-Chuan Yang

Inventor： Chia-Yu Hung ,  Chien-Ping Huang ,  Ke-Chuan Yang

IPC: H01L23/28 ,  H01L23/48

CPC classification number: H01L27/14625 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/8592 ,  H01L2924/00014

Abstract: A photosensitive semiconductor package and a method for fabricating the same are proposed. The package includes a carrier having a first surface, an opposite second surface, and an opening penetrating the carrier; a photosensitive chip having an active surface and a non-active surface, wherein a plurality of bond pads are formed close to edges of the active surface, and the chip is mounted via corner positions of its active surface to the second surface of the carrier, with the bond pads being exposed via the opening; a plurality of bonding wires formed in the opening, for electrically connecting the bond pads of the chip to the first surface of the carrier; a light-penetrable unit attached to the active surface of the chip and received in the opening; and an encapsulant for encapsulating the bonding wires and peripheral sides of the chip to seal the opening.

Abstract translation: 提出了一种光敏半导体封装及其制造方法。 该包装包括具有第一表面，相对的第二表面和穿透载体的开口的载体; 具有活性表面和非活性表面的感光芯片，其中多个接合焊盘形成在靠近有源表面的边缘处，并且芯片通过其有源表面的拐角位置安装到载体的第二表面， 接合垫通过开口露出; 形成在所述开口中的多个接合线，用于将所述芯片的接合焊盘电连接到所述载体的所述第一表面; 附着在芯片的活动表面并容纳在开口中的可透光单元; 以及用于封装芯片的接合线和周边的密封剂以密封开口。

公开(公告)号：US20050133878A1

公开(公告)日：2005-06-23

申请号：US10953915

申请日：2004-09-28

Applicant: Chien-Ping Huang

Inventor： Chien-Ping Huang

IPC: H01L21/56 ,  H01L31/0203

CPC classification number: H01L31/0203 ,  H01L23/49861 ,  H01L27/14618 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A photosensitive semiconductor package, a method for fabricating the same, and a lead frame thereof are proposed. The lead frame has a die pad and a plurality of leads, wherein at least one recessed portion is formed at an end of each lead close to the die pad, and at least one recessed region is formed on the die pad. An encapsulant fills the recessed portions, the recessed region, and between the leads and the die pad, and is formed on the lead frame to define a chip receiving cavity. A photosensitive chip is mounted in the chip receiving cavity, wherein at least partially a non-active surface of the chip is attached to the encapsulant filling the recessed region and is not in contact with the recessed region. A light-penetrable unit is attached to the encapsulant formed on the lead frame to seal the chip receiving cavity.

Abstract translation: 提出了一种光敏半导体封装及其制造方法及其引线框架。 引线框架具有管芯焊盘和多个引线，其中至少一个凹部形成在靠近管芯焊盘的每个引线的端部处，并且至少一个凹陷区域形成在管芯焊盘上。 密封剂填充凹陷部分，凹陷区域以及引线和芯片焊盘之间，并且形成在引线框架上以限定芯片接收腔。 感光芯片安装在芯片接收腔中，其中至少部分地将芯片的非活性表面附着到填充凹陷区域并且不与凹陷区域接触的密封剂。 可透光单元连接到形成在引线框架上的密封剂以密封芯片接收腔。

公开(公告)号：US20050040524A1

公开(公告)日：2005-02-24

申请号：US10909029

申请日：2004-07-30

Applicant: Han-Ping Pu ,  Chang-Fu Lin ,  Chien-Ping Huang

Inventor： Han-Ping Pu ,  Chang-Fu Lin ,  Chien-Ping Huang

IPC: H01L23/498 ,  H01L23/48

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15311

Abstract: A chip carrier for a semiconductor chip is provided. A plurality of solder pads for bump soldering are formed on a chip mounting surface of the chip carrier, to allow a flip chip to be mounted and electrically connected to the chip carrier. A solder mask layer is formed on the chip carrier, wherein a plurality of openings are provided in the solder mask layer to expose the solder pads, and an outwardly opening extended portion is formed respectively from the openings corresponding to the solder pads having a relatively narrower pitch therebetween, so as to prevent formation of voids during an underfill process for filing a gap between the flip chip and the chip carrier.

Abstract translation: 提供了一种用于半导体芯片的芯片载体。 在芯片载体的芯片安装表面上形成用于凸块焊接的多个焊盘，以允许倒装芯片安装并电连接到芯片载体。 在芯片载体上形成焊料掩模层，其中在焊料掩模层中设置多个开口以露出焊盘，并且从对应于具有相对较窄的焊盘的开口分别形成向外开口的延伸部分 间隔，以防止在底部填充过程中形成空隙，以便在倒装芯片和芯片载体之间填充间隙。

公开(公告)号：US06858931B2

公开(公告)日：2005-02-22

申请号：US10329093

申请日：2002-12-23

Applicant: Chien-Ping Huang ,  Chi-Chuan Wu ,  Jui-Yu Chuang ,  Lien-Chi Chan

Inventor： Chien-Ping Huang ,  Chi-Chuan Wu ,  Jui-Yu Chuang ,  Lien-Chi Chan

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/433 ,  H01L23/10 ,  H01L23/34

CPC classification number: H01L23/4334 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: A heat sink with a collapse structure and a semiconductor device with the heat sink are proposed, in which the heat sink is in ladder-like shape due to a height difference formed between an extending portion and an body of the heat sink, and the body has at least one surface exposed to outside of the semiconductor package. The extending portion produces collapse deformation in response to stress from engagement of molds in a molding process, so as to prevent a semiconductor chip from being damaged by the stress. The heat sink directly attached to the chip allows heat generated by the chip to pass through the extending portion to the body of the heat sink, and then the heat can be dissipated through the exposed surface of the body to the outside of the semiconductor package, so as to improve the heat dissipating efficiency.

Abstract translation: 提出了具有塌陷结构的散热器和具有散热器的半导体器件，其中散热器由于散热器的延伸部分和主体之间形成的高度差而呈阶梯状，并且主体 具有暴露于半导体封装外部的至少一个表面。 延伸部分在模制过程中响应于模具接合的应力而产生塌陷变形，以防止半导体芯片被应力损坏。 直接连接到芯片的散热片允许由芯片产生的热量穿过延伸部分到达散热体的主体，然后可以将热量通过主体的暴露表面散发到半导体封装的外部， 从而提高散热效率。

公开(公告)号：US06830957B2

公开(公告)日：2004-12-14

申请号：US10452488

申请日：2003-05-30

Applicant: Han-Ping Pu ,  Chien-Ping Huang ,  Chih-Ming Huang

Inventor： Han-Ping Pu ,  Chien-Ping Huang ,  Chih-Ming Huang

IPC: H01L2144

CPC classification number: H01L24/97 ,  H01L21/565 ,  H01L23/3128 ,  H01L2224/16 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method of fabricating BGA (Ball Grid Array) packages is proposed, which utilizes a specially-designed carrier to serve as an auxiliary tool to package semiconductor chips on substrates. The carrier is formed with a plurality of cavities respective for receiving a substrate and in communication with an injection gate, such that no injection gate is required on the substrate, thereby not restricting the trace routability on the substrate. Moreover, a two-piece type of mold is allowed being used to form a number of encapsulation bodies at one time, making the fabrication more productive and cost-effective. Furthermore, the proposed BGA fabrication method can be implemented without having to provide an air outlet in the substrate but allows the resulted encapsulation body to be free of voids to assure the quality of the packages. The proposed BGA fabrication method is therefore more advantageous to use than the prior art.

Abstract translation: 提出了一种制造BGA（球栅阵列）封装的方法，该封装采用专门设计的载体作为将半导体芯片封装在衬底上的辅助工具。 载体形成有多个腔体，分别用于接收衬底并与注入栅极连通，使得在衬底上不需要注入栅极，从而不限制衬底上的迹线布线性。 此外，允许两件式的模具一次用于形成多个包封体，使得制造更加生产和成本有效。 此外，可以实现所提出的BGA制造方法，而不必在衬底中提供空气出口，但是允许所得到的封装体没有空隙以确保包装的质量。 因此，提出的BGA制造方法比现有技术更有利于使用。

公开(公告)号：US06784019B2

公开(公告)日：2004-08-31

申请号：US10219245

申请日：2002-08-15

Applicant: Chien-Ping Huang

Inventor： Chien-Ping Huang

IPC: H01L2144

CPC classification number: B82Y15/00 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A stacked dual-chip semiconductor packaging technology is proposed for the packaging of two semiconductor chips in one single package unit. The proposed dual-chip semiconductor package is characterized by an intercrossedly-stacked dual-chip arrangement which is constructed on a specially-designed leadframe having a supporting frame; a die pad supported on the supporting frame and having a peripherally-located upper portion and a centrally-located downset portion; and a set of leads linked to the supporting frame and arranged around the die pad. By the proposed packaging technology, a first semiconductor chip is mounted within the downset portion of the die pad, while a second semiconductor chip is mounted on the upper portion of the die pad in an intercrossedly-stacked manner in relation to the first semiconductor chip. Compared to the prior art, the proposed technology allows the packaging process to be implemented in a less complex and more cost-effective manner. Moreover, since the underlying chip is attached to die pad, it allows an increased heat-dissipation efficiency to the semiconductor package.

Abstract translation: 提出了一种堆叠的双芯片半导体封装技术，用于在一个封装单元中封装两个半导体芯片。 所提出的双芯片半导体封装的特征在于跨交叠堆叠的双芯片布置，其构造在具有支撑框架的特殊设计的引线框架上; 支撑在所述支撑框架上并且具有外围定位的上部和位于中心的下降部分的管芯焊盘; 以及连接到支撑框架并且布置在管芯焊盘周围的一组引线。 通过提出的封装技术，将第一半导体芯片安装在芯片焊盘的压缩部分内，而第二半导体芯片相对于第一半导体芯片以交叉交叠的方式安装在芯片焊盘的上部。 与现有技术相比，所提出的技术允许以不那么复杂和更具成本效益的方式实现包装过程。 此外，由于底层芯片附接到管芯焊盘，因此允许对半导体封装件的散热效率提高。

公开(公告)号：US06753206B2

公开(公告)日：2004-06-22

申请号：US10289796

申请日：2002-11-07

Applicant: Chien-Ping Huang ,  Lian-Cherng Chiang ,  Michael Chang

Inventor： Chien-Ping Huang ,  Lian-Cherng Chiang ,  Michael Chang

IPC: H01L2144

CPC classification number: H01L23/4951 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48639 ,  H01L2224/48739 ,  H01L2224/48839 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A dual-chip integrated circuit package with unaligned chip arrangement and a method of manufacturing such a dual-chip integrated circuit package are provided. The dual-chip integrated circuit package includes a leadframe having a first set of leads and a second set of leads. The dual-chip integrated circuit package is used to pack two integrated circuit chips in an unaligned chip arrangement, in which the first integrated circuit chip is mounted to one side of the inner part of the first set of leads, and the second integrated circuit chip is mounted to the other side of the same in such a manner as to allow the bonding pads on the second integrated circuit chip to be positioned in the spacing formed between the two sets of leads. This unaligned chip arrangement can help facilitate the wire-bonding process for the bonding pads on the second integrated circuit chip. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the first set of bonding wires, the second set of bonding wires, the inner part of the first set of leads, and the inner part of the second set of leads. The particular structure of the dual-chip integrated circuit package allows no restriction to the relative size between the two integrated circuit chips, thus allowing flexible selection for the combination of the two integrated circuit chips. Moreover, the dual-chip integrated circuit package can help save layout space on the circuit board and offers more functionality and storage capacity.

Abstract translation: 提供了具有未对准芯片布置的双芯片集成电路封装以及制造这种双芯片集成电路封装的方法。 双芯片集成电路封装包括具有第一组引线和第二组引线的引线框架。 双芯片集成电路封装用于以未对准的芯片布置来封装两个集成电路芯片，其中第一集成电路芯片安装在第一组引线的内部的一侧，第二集成电路芯片 以这样的方式安装到其另一侧，即允许第二集成电路芯片上的接合焊盘定位在两组引线之间形成的间隔中。 这种未对准的芯片布置可以帮助促进第二集成电路芯片上的焊盘的引线接合工艺。 密封剂用于封装第一集成电路芯片，第二集成电路芯片，第一组接合线，第二组接合线，第一组引线的内部和第二组的内部 的领导。 双芯片集成电路封装的特定结构不会限制两个集成电路芯片之间的相对尺寸，因此允许灵活选择两个集成电路芯片的组合。 此外，双芯片集成电路封装可以帮助节省电路板上的布局空间，并提供更多功能和存储容量。

公开(公告)号：US06677665B2

公开(公告)日：2004-01-13

申请号：US10092808

申请日：2002-03-06

Applicant: Chien-Ping Huang

Inventor： Chien-Ping Huang

IPC: H01L23495

CPC classification number: H01L24/32 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/05613 ,  H01L2224/29007 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A dual-die integrated circuit package is provided, which can be used to pack two semiconductor dies in the same package unit. These two semiconductor dies are of the type having an array of bonding pads formed thereon. The dual-die integrated circuit package has a first leadframe and a second leadframe, each having a die pad and a plurality of leads, with the die pad being arranged at a different elevation with respect to the leads. The two semiconductor dies are mounted on the respective die pads of the two leadframes, with the bottom surface of each semiconductor die facing the bottom surface of the other, allowing the bottom surface of one semiconductor die to be separated from the die pad of the first leadframe and the bottom surface of the other semiconductor die to be separated from the die pad of the second leadframe. This dual-die integrated circuit package structure can help prevent the interface between the semiconductor die and the die pad from delamination and eliminate contamination to the semiconductor dies and also allows the manufacture to be more cost-effective to implement than the prior art.

Abstract translation: 提供了一种双管芯集成电路封装，可用于将两个半导体管芯封装在相同的封装单元中。 这两个半导体管芯具有形成在其上的接合焊盘阵列的类型。 双芯片集成电路封装具有第一引线框架和第二引线框架，每个引线框架和第二引线框架均具有管芯焊盘和多个引线，其中管芯焊盘相对于引线设置在不同的高度。 两个半导体管芯安装在两个引线框架的相应管芯焊盘上，每个半导体管芯的底表面面对另一个半导体管芯的底表面，允许一个半导体管芯的底表面与第一个半导体管芯的管芯焊盘分离 引线框架和另一半导体管芯的底表面与第二引线框架的管芯焊盘分离。 这种双管芯集成电路封装结构可以帮助防止半导体管芯和管芯焊盘之间的界面脱层，并且消除对半导体管芯的污染，并且还允许制造比现有技术更具成本效益。