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    High density three dimensional semiconductor die package
    62.
    发明授权
    High density three dimensional semiconductor die package 有权
    高密度三维半导体芯片封装

    公开(公告)号：US08653653B2

    公开(公告)日：2014-02-18

    申请号：US12648697

    申请日：2009-12-29

    申请人： Cheeman Yu ,  Chih-Chin Liao ,  Hem Takiar

    发明人： Cheeman Yu ,  Chih-Chin Liao ,  Hem Takiar

    IPC分类号： H01L23/34

    CPC分类号： H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C5/143 ,  G11C8/12 ,  H01L21/485 ,  H01L23/5382 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die.

    摘要翻译： 公开了一种半导体封装，其包括安装在基板的堆叠和接合层上的多个半导体管芯，例如在带自动焊接工艺中使用的聚酰亚胺带。 带可以具有多个重复图案的迹线和形成在其上的接触垫。 每个迹线包括在衬底的相应顶部和底部表面上的对准的互连焊盘，用于在将图案从基板切割成对准和堆叠之后将一个图案的迹线粘合到另一图案的迹线。 诸如闪速存储器和控制器管芯的半导体管芯安装在衬底上各个图案的迹线上。 为了使控制器裸片独特地寻址堆叠中的特定闪存芯片，支持存储芯片的每个衬底上的一组迹线被用作地址引脚，并相对于其它衬底的迹线的布局以独特的布局冲压。 通过在基板上提供具有唯一的地址迹线布局的每个闪速存储器半导体管芯，每个存储管芯可以被控制器管芯选择性地寻址。

    GLOB TOP SEMICONDUCTOR PACKAGE
    65.
    发明申请
    GLOB TOP SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20120193802A1

    公开(公告)日：2012-08-02

    申请号：US13019126

    申请日：2011-02-01

    申请人： Chin-Tien Chiu ,  Chih-Chin Liao ,  Peng Fu

    发明人： Chin-Tien Chiu ,  Chih-Chin Liao ,  Peng Fu

    IPC分类号： H01L23/48

    CPC分类号： H01L23/24 ,  H01L21/56 ,  H01L23/3121 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012

    摘要： A semiconductor package is disclosed including a substrate, a solder mask layer, one or more semiconductor die mounted to the solder mask layer and electrically coupled to the substrate, and a glob top cover over the semiconductor die. The solder mask further includes a dam protruding above surrounding areas of the solder mask layer and a cavity recessed into the solder mask layer for limiting flow of the glob top cover when the glob top material is applied.

    摘要翻译： 公开了一种半导体封装，其包括衬底，焊接掩模层，安装到焊料掩模层并电耦合到衬底的一个或多个半导体管芯以及半导体管芯上的球顶盖。 焊料掩模还包括突出在焊料掩模层的周围区域上方的坝体和凹入焊料掩模层中的空腔，用于限制球形顶盖材料施加时球体顶盖的流动。

    Integrated-circuit package with a quick-to-count finger layout design on substrate
    68.
    发明授权
    Integrated-circuit package with a quick-to-count finger layout design on substrate 有权
    集成电路封装，在基板上具有快速计数的手指布局设计

    公开(公告)号：US06465891B2

    公开(公告)日：2002-10-15

    申请号：US09766476

    申请日：2001-01-19

    申请人： Wen-Hsin Wang ,  Chih-Chin Liao

    发明人： Wen-Hsin Wang ,  Chih-Chin Liao

    IPC分类号： H01L2348

    CPC分类号： H01L24/49 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48237 ,  H01L2224/49171 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/00014

    摘要： An integrated-circuit package with a quick-to-count finger layout design on substrate is proposed, which can help fabrication engineers to visually check the total number of fingers on the substrate in a quick and accurate manner. The proposed integrated-circuit package is characterized by the provision of a line-up array of fingers which includes a plurality of first-shape fingers partitioned equally in number into a plurality of subgroups; and a plurality of second-shape fingers, which are substantially visually distinguishable in outer appearance from the first-shape fingers, and which are interposed between adjacent subgroups of the first-shape fingers to serve as count tokens. This finger layout design allows the fabrication engineers to visually check the total number of the line-up array of fingers on the substrate simply by counting through the second-shape fingers that serve as count tokens and then multiply the result by the number of first-shape fingers in each subgroup plus one.

    摘要翻译： 提出了一种在基板上具有快速计数手指布局设计的集成电路封装，可以帮助制造工程师以快速准确的方式目视检查基板上的手指总数。 所提出的集成电路封装的特征在于提供一个阵列阵列的指状阵列，其包括多个分成多个子组的数个等分的第一形状的指状物; 以及多个第二形状的手指，其在外观上与第一形状指状件基本上在视觉上可区分，并且被插入在第一形状指状物的相邻子组之间用作计数令牌。 这种手指布局设计允许制造工程师通过仅通过用作计数令牌的第二形手指计数，然后将结果乘以第一形状的数量，目视地检查基板上的指状阵列的总数， 每个子组中的形状手指加一个。

    Method of fabricating plated circuit lines over ball grid array substrate
    69.
    发明授权
    Method of fabricating plated circuit lines over ball grid array substrate 失效
    在球栅阵列基板上制造电镀电路线的方法

    公开(公告)号：US06399417B1

    公开(公告)日：2002-06-04

    申请号：US09837959

    申请日：2001-04-19

    申请人： Wen Cheng Lee ,  Chih-Chin Liao

    发明人： Wen Cheng Lee ,  Chih-Chin Liao

    IPC分类号： H01L2144

    CPC分类号： H05K3/242 ,  H01L21/4846 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K3/0047 ,  H05K2203/1572 ,  H05K2203/175 ,  H01L2924/00014

    摘要： A method is proposed for the fabrication of plated circuit lines, including contact fingers, electrically-conductive traces, and solder-ball pads, over an BGA (Ball Grid Array) substrate. The method is characterized by that contact fingers, electrically-conductive traces, and solder-ball pads on the BGA substrate are interconnected with provisional bridging lines; and then, each integrally-connected group of the contact fingers, the electrically-conductive traces, and the solder-ball pads is connected via a branched plating line to a common plating bus. During plating process, the plating electrical current can be applied to the plating bus and then distributed over these branched plating lines to all of the contact fingers and the solder-ball pads. Finally, a drilling process is performed to break all the provisional bridging lines into open-circuited state. Compared to the prior art, since the proposed method requires no use of etchant during the drilling process, it would cause no contamination to the substrate surfaces. Moreover, the proposed method allows the use of a reduced layout area for the circuit lines and can help reduce mutual inductive interference among the circuit lines.

    摘要翻译： 提出了一种用于在BGA（球栅阵列）衬底上制造包括接触指状物，导电迹线和焊球焊盘的电镀电路线的方法。 该方法的特征在于，BGA衬底上的接触指状物，导电迹线和焊球焊盘与临时桥接线互连; 然后，每个整体连接的接触指的组，导电迹线和焊球焊盘通过分支电镀线连接到公共电镀母线。 在电镀过程中，电镀电流可以施加到电镀母线上，然后分布在这些分支电镀线上，到所有接触指和焊球垫。 最后，进行钻井过程以将所有临时桥接线路断开为断路状态。 与现有技术相比，由于所提出的方法在钻井过程中不需要使用蚀刻剂，因此不会对基材表面产生污染。 此外，所提出的方法允许对电路线路使用减少的布局面积，并且可以帮助减少电路线路之间的互感干扰。