公开(公告)号：US20190326409A1

公开(公告)日：2019-10-24

申请号：US15956926

申请日：2018-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/266 ,  H01L27/11 ,  H01L21/3105 ,  H01L29/08 ,  H01L29/786

Abstract: The present disclosure relates to manufacturing techniques and respective semiconductor devices in which the capping material of gate electrode structures may be removed together with portions of the capping material of resistors on the basis of a highly controllable directional etch process, wherein raised drain and source regions may be protected on the basis of a fill material.

公开(公告)号：US10347543B2

公开(公告)日：2019-07-09

申请号：US15810557

申请日：2017-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Rick Carter ,  Vikrant Chauhan ,  George Jonathan Kluth ,  Anurag Mittal ,  David Pritchard ,  Mahbub Rashed

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L27/12 ,  H01L29/49

Abstract: A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding raised source/drain regions.

公开(公告)号：US10224251B2

公开(公告)日：2019-03-05

申请号：US15667017

申请日：2017-08-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Gunter Grasshoff

IPC: H01L21/84 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L27/12

Abstract: When forming sophisticated semiconductor devices requiring resistors based on polysilicon material having non-silicided portions, the respective cap material for defining the silicided portions may be omitted during the process sequence, for instance, by using a patterned liner material or by applying a process strategy for removing the metal material from resistor areas that may not receive a corresponding metal silicide. By implementing the corresponding process strategies, semiconductor devices may be obtained with reduced probability of contact failures, with superior performance due to relaxing surface topography upon forming the contact level, and/or with increased robustness with respect to contact punch-through.

公开(公告)号：US10079300B2

公开(公告)日：2018-09-18

申请号：US15426728

申请日：2017-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Carsten Grass

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/1159 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/28185 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/40111 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor circuit element includes a first semiconductor device positioned in and above a first active region of a semiconductor substrate and a second semiconductor device positioned in and above a second active region of the semiconductor substrate. The first semiconductor device includes a first gate structure having a first gate dielectric layer that includes a first high-k material, and the second semiconductor device includes a second gate structure having a second gate dielectric layer that includes a ferroelectric material that is different from the first high-k material.

公开(公告)号：US10056369B1

公开(公告)日：2018-08-21

申请号：US15890452

申请日：2018-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Frank Jakubowski

IPC: H01L21/00 ,  H01L27/06 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/84 ,  H01L21/762 ,  H01L49/02 ,  H01L29/49 ,  H01L23/31 ,  H01L29/417 ,  H01L23/535 ,  H01L29/06 ,  H01L27/12 ,  H01L27/108

Abstract: A method includes forming a plurality of openings extending through a semiconductor layer, through a buried insulating layer, and into a substrate material in a second device region of a semiconductor device while covering a first device region of the semiconductor device. An insulating material is formed on sidewalls and on a bottom face of each of the plurality of openings, and a first capacitor electrode is formed in each of the plurality of openings in the presence of the insulating material, wherein each of the first capacitor electrodes includes a conductive material and partially fills a respective one of the plurality of openings.

公开(公告)号：US10032891B2

公开(公告)日：2018-07-24

申请号：US15498652

申请日：2017-04-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Juergen Faul

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L29/78 ,  H01L27/115 ,  H01L27/088 ,  H01L21/266 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/11536 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/11521

Abstract: A method of manufacturing a flash memory cell is provided including forming a plurality of semiconductor fins on a semiconductor substrate, forming floating gates for a sub-set of the plurality of semiconductor fins and forming a first insulating layer between the plurality of semiconductor fins. The first insulating layer is recessed to a height less than the height of the plurality of semiconductor fins and sacrificial gates are formed over the sub-set of the plurality of semiconductor fins. A second insulating layer is formed between the sacrificial gates and, after that, the sacrificial gates are removed. Recesses are formed in the first insulating layer and sense gates and control gates are formed in the recesses for the sub-set of the plurality of semiconductor fins. The first and second insulating layers may be oxide layers.

公开(公告)号：US20180061839A1

公开(公告)日：2018-03-01

申请号：US15252995

申请日：2016-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Jürgen Thees

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L27/12 ,  H01L29/66 ,  H01L21/762 ,  H01L21/285 ,  H01L21/84 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L27/10811 ,  H01L21/28518 ,  H01L21/76283 ,  H01L21/76897 ,  H01L21/84 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/1203 ,  H01L28/82 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7838 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device structure is disclosed including a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer, a substrate material and a buried insulating material layer positioned between the semiconductor layer and the substrate material, a trench isolation structure positioned in at least a portion of the SOI substrate, the trench isolation structure defining a first region in the SOI substrate, and a capacitor device formed in the first region, the capacitor device comprising a first electrode formed by a conductive layer portion formed in the first region on the buried insulating material layer, the conductive layer portion at least partially replacing the semiconductor layer in the first region, a second electrode formed over the first electrode, and an insulating material formed between the first electrode and the second electrode.

公开(公告)号：US09806170B1

公开(公告)日：2017-10-31

申请号：US15151550

申请日：2016-05-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Rick J. Carter ,  Peter Baars ,  Hans-Jürgen Thees ,  Jan Höntschel

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/7838

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

公开(公告)号：US20170162557A1

公开(公告)日：2017-06-08

申请号：US14958150

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Juergen Faul

IPC: H01L27/02 ,  H01L29/66 ,  H01L21/84 ,  H01L29/417 ,  H01L27/12 ,  H01L27/07 ,  H01L49/02

CPC classification number: H01L27/0222 ,  G05F3/205 ,  H01L27/1203 ,  H01L27/13 ,  H01L28/40 ,  H01L29/665 ,  H01L29/945

Abstract: A semiconductor device is provided including a fully depleted silicon-on-insulator (FDSOI) substrate and a charge pump device, wherein the FDSOI substrate comprises a semiconductor bulk substrate, and the charge pump device comprises a transistor device formed in and on the FDSOI substrate, and a trench capacitor formed in the semiconductor bulk substrate and electrically connected to the transistor device. A semiconductor device is further provided including a semiconductor bulk substrate, a first transistor device comprising a first source/drain region, a second transistor device comprising a second source/drain region, a first trench capacitor comprising a first inner capacitor electrode and a first outer capacitor electrode, and a second trench capacitor comprising a second inner capacitor electrode and a second outer capacitor electrode, wherein the first inner capacitor electrode is connected to the first source/drain region and the second inner capacitor electrode is connected to the second source/drain region.

公开(公告)号：US09666589B1

公开(公告)日：2017-05-30

申请号：US15075352

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Juergen Faul

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/11541 ,  H01L27/11521 ,  H01L27/11536

CPC classification number: H01L29/66825 ,  H01L21/266 ,  H01L21/7684 ,  H01L21/76883 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0886 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881

Abstract: A method of manufacturing a semiconductor device is provided including providing a semiconductor substrate, forming a first plurality of semiconductor fins in a logic area of the semiconductor substrate, forming a second plurality of semiconductor fins in a memory area of the semiconductor substrate, forming an insulating layer between the fins of the first plurality of semiconductor fins and between the fins of the second plurality of semiconductor fins, forming an electrode layer over the first and second pluralities of semiconductor fins and the insulating layer, forming gates over semiconductor fins of the first plurality of semiconductor fins in the logic area from the gate electrode layer, and forming sense gates and control gates between semiconductor fins of the second plurality of semiconductor fins in the logic area from the gate electrode layer.