公开(公告)号：US09786667B2

公开(公告)日：2017-10-10

申请号：US15474689

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20160133699A1

公开(公告)日：2016-05-12

申请号：US14942274

申请日：2015-11-16

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/267 ,  H01L29/775 ,  H01L29/165 ,  H01L29/205 ,  H01L29/08

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/7391 ,  H01L29/772 ,  H01L29/775

Abstract: An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band. Other embodiments are described herein.

Abstract translation: 一个实施例包括一个包括源极，沟道和漏极的异质结隧道场效应晶体管; 其中（a）所述通道包括对应于通道长度的长轴和对应于通道宽度并与所述长轴正交的短轴; （b）通道长度小于10nm; （c）源极掺杂第一极性并具有第一导带; （d）漏极掺杂有与第一极性相反的第二极性，并且漏极具有比第一导带具有更高能量的第二导带。 本文描述了其它实施例。

公开(公告)号：US20250113599A1

公开(公告)日：2025-04-03

申请号：US18477414

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Kirby Maxey ,  Pratyush P. Buragohain ,  Chelsey Dorow ,  Mahmut Sami Kavrik ,  Wouter Mortelmans ,  Marko Radosavljevic ,  Uygar E. Avci ,  Matthew V. Metz

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/26 ,  H01L29/66 ,  H01L29/775

Abstract: Methods for doping 2D transistor devices and resulting architectures. The use and placement of oxide dopants, such as, but not limited to, GeOx, enable control over threshold voltage performance and contact resistance of 2D transistor devices. Architectures include distinct stoichiometry compositions.

公开(公告)号：US20240355934A1

公开(公告)日：2024-10-24

申请号：US18304659

申请日：2023-04-21

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Tristan A. Tronic ,  Jennifer Lux ,  Uygar E. Avci ,  Kevin P. O'Brien

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/66969 ,  H01L29/0847 ,  H01L29/24

Abstract: Described herein are transistors with monolayer transition metal dichalcogenides (TMD) semiconductor material. TMD materials include combination of a transition metal (e.g., molybdenum or tungsten) and a chalcogen (e.g., sulfur or selenium) in a monolayer having a hexagonal crystal structure. A transistor has a single layer of TMD forming a channel region, and multiple layers of the TMD material at the source and drain regions. Upper portions of the multilayer TMD source and drain regions are doped, and conductive contacts are formed over the doped portions.

公开(公告)号：US20240114694A1

公开(公告)日：2024-04-04

申请号：US17937043

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sourav Dutta ,  Nazila Haratipour ,  Uygar E. Avci ,  Vachan Kumar ,  Christopher M. Neumann ,  Shriram Shivaraman ,  Sou-Chi Chang ,  Brian S. Doyle

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: Backside integrated circuit capacitor structures. In an example, a capacitor structure includes a layer of ferroelectric material between first and second electrodes. The first electrode can be connected to a transistor terminal by a backside contact that extends downward from a bottom surface of the transistor terminal to the first electrode. The transistor terminal can be, for instance, a source or drain region, and the backside contact can be self-aligned with the source or drain region. The second electrode can be connected to a backside interconnect feature. In some cases, the capacitor has a height that extends through at least one backside interconnect layer. In some cases, the capacitor is a multi-plate capacitor in which the second conductor is one of a plurality of plate line conductors arranged in a staircase structure. The capacitor structure may be, for example, part of a non-volatile memory device or the cache of a processor.

公开(公告)号：US20240114692A1

公开(公告)日：2024-04-04

申请号：US17958395

申请日：2022-10-01

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Uygar E. Avci ,  Vachan Kumar ,  Hai Li ,  Yu-Ching Liao ,  Ian Alexander Young

IPC: H01L27/11502 ,  G11C11/22 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L27/11502 ,  G11C11/221 ,  G11C11/223 ,  H01L27/1087 ,  H01L29/945

Abstract: Inverted pillar capacitors that have a U-shaped insulating layer are oriented with the U-shaped opening of the insulating layer opening toward the surface of the substrate on which the inverted pillar capacitors are formed. The bottom electrodes of adjacent inverted pillar capacitors are isolated from each other by the insulating layers of the adjacent electrodes and the top electrode that fills the volume between the electrodes. By avoiding the need to isolate adjacent bottom electrodes by an isolation dielectric region, inverted pillar capacitors can provide for a greater capacitor density relative to non-inverted pillar capacitors. The insulating layer in inverted pillar capacitors can comprise a ferroelectric material or an antiferroelectric material. The inverted pillar capacitor can be used in memory circuits (e.g., DRAMs) or non-memory applications.

公开(公告)号：US20240113101A1

公开(公告)日：2024-04-04

申请号：US17936990

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sourav Dutta ,  Nazila Haratipour ,  Vachan Kumar ,  Uygar E. Avci ,  Shriram Shivaraman ,  Sou-Chi Chang

IPC: H01L27/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L28/55 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/778 ,  H01L29/0673

Abstract: Techniques are provided herein to form a semiconductor device that has a capacitor structure integrated with the source or drain region of the semiconductor device. A given semiconductor device includes one or more semiconductor regions extending in a first direction between corresponding source or drain regions. A gate structure extends in a second direction over the one or more semiconductor regions. A capacitor structure is integrated with one of the source or drain regions of the integrated circuit such that a first electrode of the capacitor contacts the source or drain region and a second electrode of the capacitor contacts a conductive contact formed over the capacitor structure. The capacitor structure may include a ferroelectric capacitor having a ferroelectric layer between the electrodes.

公开(公告)号：US20230420364A1

公开(公告)日：2023-12-28

申请号：US17849207

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Tristan A. Tronic ,  Ande Kitamura ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Chelsey Dorow ,  Kirby Maxey ,  Scott B. Clendenning ,  Sudarat Lee ,  Uygar E. Avci

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/423 ,  H01L29/18 ,  H01L27/092 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L29/42392 ,  H01L29/18 ,  H01L27/0924 ,  H01L29/78696 ,  H01L29/66742

Abstract: A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; a first structure on the substrate, the first structure corresponding to a front end of line (FEOL) stack of the device and including a plurality of first transistors therein; and a second structure on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the device, and including a plurality of second transistors therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material. The second transistors are part of a voltage regulation architecture to regulate voltage supply to the die.

公开(公告)号：US20230200079A1

公开(公告)日：2023-06-22

申请号：US17555207

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Tanay A. Gosavi ,  Uygar E. Avci ,  Sou-Chi Chang ,  Hai Li ,  Dmitri Evgenievich Nikonov ,  Kaan Oguz ,  Ashish Verma Penumatcha ,  John J. Plombon ,  Ian Alexander Young

IPC: H01L27/11514 ,  H01L49/02 ,  H01L29/51

CPC classification number: H01L27/11514 ,  H01L28/65 ,  H01L29/516

Abstract: A first type of ferroelectric capacitor comprises electrodes and an insulating layer comprising ferroelectric oxides. In some embodiments, the electrodes and the insulating layer comprise perovskite ferroelectric oxides. A second type of ferroelectric capacitor comprises a ferroelectric insulating layer comprising certain monochalcogenides. Both types of ferroelectric capacitors can have a coercive voltage that is less than one volt. Such capacitors are attractive for use in low-voltage non-volatile embedded memories for next-generation semiconductor manufacturing technologies.

公开(公告)号：US20230058938A1

公开(公告)日：2023-02-23

申请号：US17409483

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dmitri Evgenievich Nikonov ,  Hai Li ,  Chia-Ching Lin ,  Raseong Kim ,  Tanay A. Gosavi ,  Ashish Verma Penumatcha ,  Uygar E. Avci ,  Marko Radosavljevic ,  Ian Alexander Young

IPC: G11C11/22 ,  H01L27/1159

Abstract: A pbit device, in one embodiment, includes a first field-effect transistor (FET) that includes a source region, a drain region, a source electrode on the source region, a drain electrode on the drain region, a channel region between the source and drain regions, a dielectric layer on a surface over the channel region, an electrode layer above the dielectric layer, and a ferroelectric (FE) material layer between the dielectric layer and the electrode layer. The pbit device also includes a second FET comprising a source electrode, a drain electrode, and a gate electrode. The drain electrode of the second FET is connected to the drain electrode of the first FET.