公开(公告)号：US10483361B1

公开(公告)日：2019-11-19

申请号：US16115955

申请日：2018-08-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Christopher J. Waskiewicz ,  Alexander Reznicek ,  Hemanth Jagannathan

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/45 ,  H01L27/088 ,  H01L29/78 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/321

Abstract: A method is presented for forming a wrap-around-contact. The method includes forming a bottom source/drain region adjacent a plurality of fins, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, and for forming top spacers adjacent the top portions of the plurality of fins. The method further includes disposing a sacrificial liner adjacent the encapsulation layers, recessing the top spacers, forming top source/drain regions over the top portions of the plurality of fins, removing the sacrificial liner to create trenches adjacent the top source/drain regions, and depositing a metal liner within the trenches and over the top source/drain regions such that the wrap-around-contact is defined to cover an upper area of the top source/drain regions.

公开(公告)号：US09997454B2

公开(公告)日：2018-06-12

申请号：US15358701

申请日：2016-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marc A. Bergendahl ,  James J. Demarest ,  Christopher J. Penny ,  Christopher J. Waskiewicz

IPC: H01L21/00 ,  H01L23/525 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5256 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295

Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.

公开(公告)号：US09780027B2

公开(公告)日：2017-10-03

申请号：US15160546

申请日：2016-05-20

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  James J. Demarest ,  Christopher J. Penny ,  Christopher J. Waskiewicz

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/0276 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

Abstract: A technique relates to an airgap structure. A dielectric layer is formed on an underlying layer. Copper filled trenches are formed in the dielectric layer, and a metal liner lines the copper filled trenches. An oxide liner lines the metal liner and covers the dielectric layer. One or more airgaps are formed between the copper filled trenches in areas in which the oxide liner was not present on the dielectric layer. A cap layer is formed on top of the one or more airgaps, the copper filled trenches, and portions of the oxide liner.

公开(公告)号：US20170243822A1

公开(公告)日：2017-08-24

申请号：US15479922

申请日：2017-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marc A. Bergendahl ,  James J. Demarest ,  Christopher J. Penny ,  Christopher J. Waskiewicz

IPC: H01L23/525 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5256 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295

Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.

公开(公告)号：US09449871B1

公开(公告)日：2016-09-20

申请号：US14944355

申请日：2015-11-18

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  James J. Demarest ,  Christopher J. Penny ,  Christopher J. Waskiewicz

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/027 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/0276 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

Abstract: A technique relates to an airgap structure. A dielectric layer is formed on an underlying layer. Copper filled trenches are formed in the dielectric layer, and a metal liner lines the copper filled trenches. An oxide liner lines the metal liner and covers the dielectric layer. One or more airgaps are formed between the copper filled trenches in areas in which the oxide liner was not present on the dielectric layer. A cap layer is formed on top of the one or more airgaps, the copper filled trenches, and portions of the oxide liner.

Abstract translation: 技术涉及气隙结构。 介电层形成在下层上。 在电介质层中形成铜填充的沟槽，并且金属衬垫对铜填充的沟槽进行排列。 氧化物衬垫使金属衬里线上并覆盖电介质层。 在电介质层上不存在氧化物衬垫的区域中的铜填充沟槽之间形成一个或多个气隙。 在一个或多个气隙，铜填充沟槽和氧化物衬垫的部分的顶部上形成盖层。

公开(公告)号：US20140199832A1

公开(公告)日：2014-07-17

申请号：US13741638

申请日：2013-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Son V. Nguyen ,  Tuan A. Vo ,  Christopher J. Waskiewicz

IPC: H01L21/48

CPC classification number: H01L21/76802 ,  H01L21/02186 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02258 ,  H01L21/02326 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/486 ,  H01L21/76811 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A vertical stack including a dielectric hard mask layer and a titanium nitride layer is formed over an interconnect-level dielectric material layer such as an organosilicate glass layer. The titanium nitride layer may be partially or fully converted into a titanium oxynitride layer, which is subsequently patterned with a first pattern. Alternately, the titanium nitride layer, with or without a titanium oxynitride layer thereupon, may be patterned with a line pattern, and physically exposed surface portions of the titanium nitride layer may be converted into titanium oxynitride. Titanium oxynitride provides etch resistance during transfer of a combined first and second pattern, but can be readily removed by a wet etch without causing surface damages to copper surfaces. A chamfer may be formed in the interconnect-level dielectric material layer by an anisotropic etch that employs any remnant portion of titanium nitride as an etch mask.

Abstract translation: 在诸如有机硅酸盐玻璃层的互连层电介质材料层上形成包括电介质硬掩模层和氮化钛层的垂直叠层。 氮化钛层可以部分地或完全地转化成氮氧化钛层，其随后用第一图案图案化。 或者，可以用线图案来图案化具有或不具有氮氧化钛层的氮化钛层，并且氮化钛层的物理暴露的表面部分可以转化为氮氧化钛。 钛氮氧化合物在组合的第一和第二图案的转印期间提供耐蚀刻性，但是可以通过湿蚀刻容易地除去而不会对铜表面造成表面损伤。 可以通过使用氮化钛的任何残余部分作为蚀刻掩模的各向异性蚀刻在互连级介电材料层中形成倒角。

公开(公告)号：US20240321630A1

公开(公告)日：2024-09-26

申请号：US18187738

申请日：2023-03-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Christopher J. Waskiewicz ,  Chih-Chao Yang ,  Huai Huang ,  Koichi Motoyama ,  Julien Frougier

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53252

Abstract: A semiconductor structure including first metal lines embedded in a first dielectric layer, second metal lines embedded in a second dielectric layer, where the second metal lines arranged above the first metal lines, a top via extending between one of the first metal lines and one of the second metal lines, where the top via is self-aligned to the one of the first metal lines, and at least one air gap located adjacent to the top via between the first metal lines and the second metal lines.

公开(公告)号：US11742350B2

公开(公告)日：2023-08-29

申请号：US17482504

申请日：2021-09-23

Applicant: International Business Machines Corporation

Inventor： Andrew Gaul ,  Chanro Park ,  Julien Frougier ,  Ruilong Xie ,  Andrew M. Greene ,  Christopher J. Waskiewicz

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/823878

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures that provide metal gate N/P boundary control in an integrated circuit (IC) using an active gate cut and recess processing scheme. In a non-limiting embodiment of the invention, a gate cut is formed in an N/P boundary between an n-type field effect transistor (FET) and a p-type FET. A first portion of a first work function metal is removed over a channel region of the n-type FET. The gate cut prevents etching a second portion of the first work function metal. The first portion of the first work function metal is replaced with a second work function metal. The gate cut is recessed, and a conductive region is formed on the recessed surface of the gate cut. The conductive region provides electrical continuity across the N/P boundary.

公开(公告)号：US11742246B2

公开(公告)日：2023-08-29

申请号：US17502210

申请日：2021-10-15

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Hemanth Jagannathan ,  Christopher J. Waskiewicz ,  Alexander Reznicek

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical field effect transistor structure and method for fabricating the same. The structure includes a source/drain layer in contact with at least one semiconductor fin. An edge portion of the source/drain layer includes a notched region filled with a dielectric material. A spacer layer includes a first portion in contact with the source/drain layer and a second portion in contact with the dielectric material. A gate structure contacts the spacer layer and the dielectric material. The method includes forming a source/drain layer in contact with at least one semiconductor fin. A spacer layer is formed in contact with the source/drain layer. A portion of the spacer layer is removed to expose an end portion of the source/drain layer. The exposed end portion of the source/drain layer is recessed to form a notched region within the source/drain layer. A dielectric layer is formed within the notched region.

公开(公告)号：US20230197531A1

公开(公告)日：2023-06-22

申请号：US17554249

申请日：2021-12-17

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Christopher J. Penny ,  James John Demarest ,  Jean Wynne ,  Christopher J. Waskiewicz ,  Jonathan Fry

IPC: H01L21/66 ,  H01L23/498

CPC classification number: H01L22/12 ,  H01L23/49822 ,  H01L23/49827

Abstract: Embodiments of the invention provide a method that includes forming an IC layer having an inactive region and an active region. The active region includes a device-under-fabrication (DUF). The inactive region includes a geometric feature having a geometric shape. A film is deposited over the active DUF and the geometric feature such that a first portion of the film will be part of the active DUF, and such that a second portion of the film is over the geometric feature. A geometric shape of the film over the geometric feature matches the geometric shape of the geometric feature. Determining a thickness of the film is based at least in part a difference between a footprint of the geometric shape of the film and a footprint of the geometric shape of the geometric feature.