公开(公告)号：US20060064999A1

公开(公告)日：2006-03-30

申请号：US10954379

申请日：2004-09-29

申请人： Jim Hermerding ,  Barnes Cooper ,  Steve Frayne ,  Eric Distefano ,  Sridhar Machiroutu

发明人： Jim Hermerding ,  Barnes Cooper ,  Steve Frayne ,  Eric Distefano ,  Sridhar Machiroutu

IPC分类号： F24F7/00 ,  F25D23/12 ,  H01L23/06 ,  H01L23/15

CPC分类号： G06F1/3203 ,  G06F1/206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16

摘要： A method of creating a thermal influence table to describe thermal relationships between components in a system and use of the thermal influence table in a system is described. The thermal influence matrix may be generated dynamically for a system. The matrix may be used by a thermal management policy to enable a hot device to be cooled by power management of another device in the system.

公开(公告)号：US20050086547A1

公开(公告)日：2005-04-21

申请号：US10681446

申请日：2003-10-06

申请人： Grant Kobayashi ,  Barnes Cooper

发明人： Grant Kobayashi ,  Barnes Cooper

IPC分类号： G06F9/445 ,  G06F9/48 ,  G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/4401

摘要： A method and apparatus for efficient memory allocation and system management interrupt (SMI) handling is herein described. Upon waking a second processor in a multiple processor system, one may use a single SMI to initialize each processor, may use the location of a single default SMI handler as a wake-up vector to the second processor, and may patch an instruction pointer to a non-aligned address during the handling of the SMI with the second processor to forgo the traditional extra aligned memory allocation. In addition, one may use unified handler code to handle software generated SMIs on both the first and second processors and may use exit SMM directly after handling a hardware SMI to save execution time.

摘要翻译： 这里描述了用于高效存储器分配和系统管理中断（SMI）处理的方法和装置。 当在多处理器系统中唤醒第二处理器时，可以使用单个SMI来初始化每个处理器，可以将单个默认SMI处理器的位置用作到第二处理器的唤醒向量，并且可以将指令指针 在处理SMI期间使用第二处理器来放弃传统的额外对齐的存储器分配的非对齐地址。 此外，可以使用统一的处理程序代码来处理第一和第二处理器上的软件生成的SMI，并且可以在处理硬件SMI之后直接使用退出SMM来节省执行时间。

公开(公告)号：US06829713B2

公开(公告)日：2004-12-07

申请号：US09751759

申请日：2000-12-30

申请人： Barnes Cooper ,  Jay Arjangrad

发明人： Barnes Cooper ,  Jay Arjangrad

IPC分类号： G06F132

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  Y02D10/128

摘要： A demand-based method and system of central processing unit power management. The utilization of a central processing unit (CPU) during a sampling time interval is determined by measuring a time quantum within the sampling time interval during which a central processing unit clock signal is active within a processor core of the CPU. The total number of cycles of the central processing unit clock signal that are applied to the processor core and the period of the central processing unit clock signal are used to determine the time quantum. The utilization may then be expressed in terms of a ratio of the time quantum to the total time interval and used to select a processor performance mode. The CPU is then operated in the selected processor performance mode.

摘要翻译： 中央处理单元电源管理的基于需求的方法和系统。 在采样时间间隔期间利用中央处理单元（CPU）通过测量在CPU的处理器核心内的中央处理单元时钟信号有效的采样时间间隔内的时间量度来确定。 使用施加到处理器核心的中央处理单元时钟信号的周期数和中央处理单元时钟信号的周期来确定时间量。 然后利用率可以用时间量与总时间间隔的比率来表示，并用于选择处理器性能模式。 然后CPU以选定的处理器性能模式运行。

公开(公告)号：US06792491B2

公开(公告)日：2004-09-14

申请号：US10027653

申请日：2001-12-21

申请人： Barnes Cooper

发明人： Barnes Cooper

IPC分类号： G06F1324

CPC分类号： G06F13/24

摘要： In one embodiment of the invention, an embedded controller receives an interrupt command and a query number from a system management interrupt (SMI) handler. The embedded controller generates a system control interrupt (SCI) in response to the interrupt command. A driver that receives the SCI issues a query command to the embedded controller. A routine associated with the query number is invoked in response to the query command.

摘要翻译： 在本发明的一个实施例中，嵌入式控制器从系统管理中断（SMI）处理器接收中断命令和查询号。 嵌入式控制器响应于中断命令产生系统控制中断（SCI）。 接收SCI的驱动程序向嵌入式控制器发出查询命令。 响应查询命令调用与查询号相关联的例程。

公开(公告)号：US06738068B2

公开(公告)日：2004-05-18

申请号：US09751441

申请日：2000-12-29

申请人： Debra T. Cohen ,  Leslie E. Cline ,  Barnes Cooper ,  Satchit Jain ,  Anil V. Nanduri

发明人： Debra T. Cohen ,  Leslie E. Cline ,  Barnes Cooper ,  Satchit Jain ,  Anil V. Nanduri

IPC分类号： G06F1314

CPC分类号： G06T17/00 ,  G06F1/3203

摘要： An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

摘要翻译： 加速图形端口图形控制器（AGP-GC）和核心控制器之间的接口，以防止进入低功率状态，干扰来自AGP-GC的请求但尚未完成的传输。 核心控制器可以与AGP-GC进行通信，意图进入低功率状态，而AGP-GC可以与核心控制器通信AGP-GC的忙碌状态。 当AGP-GC接收到进入低功率状态的意图时，可以停止向核心控制器发出请求。 当核心控制器检测到AGP-GC正忙时，核心控制器可以推迟进入低功率状态，直到AGP-GC完成任何正在进行的请求。 在接口的替代使用中，如果AGP-GC希望在低功率状态期间发出请求，则可以通过指示忙状态来向核心控制器通知该核心控制器，这可以触发核心控制器发起退出 低功率状态。

公开(公告)号：US06446153B1

公开(公告)日：2002-09-03

申请号：US08818048

申请日：1997-03-14

申请人： Barnes Cooper ,  James Kardach

发明人： Barnes Cooper ,  James Kardach

IPC分类号： G06F946

摘要： A computer system is described where one or more processors executing operating system (OS) code and System Management (SM) code can access the same host interface of an embedded controller. The embedded controller, in turn, is coupled to one or more system devices such as an IDE power plane switch, a thermal A/D monitor, a System Management Bus (SMBus), etc. The embedded controller asserts a system management interrupt (SMI) to the system management environment of the processing unit(s) as well as a system control interrupt to the operating system environment of the processing unit(s). Accordingly, the processing unit(s) executing operating system code and system management code is able to control and/or monitor a number of system devices in the computer system by communicating with the embedded controller via its host interface and interrupts.

公开(公告)号：US20190033953A1

公开(公告)日：2019-01-31

申请号：US15819552

申请日：2017-11-21

申请人： Vijaykumar B. Kadgi ,  Barnes Cooper ,  Nivedita Aggarwal ,  Venkataramani Gopalakrishnan ,  Jenn Chuan Cheng ,  Basavaraj Astekar ,  Charuhasini Sunderraman ,  Han Kung Chua ,  Anil Baby ,  Tin-Cheung Kung ,  Chia-Hung Kuo

发明人： Vijaykumar B. Kadgi ,  Barnes Cooper ,  Nivedita Aggarwal ,  Venkataramani Gopalakrishnan ,  Jenn Chuan Cheng ,  Basavaraj Astekar ,  Charuhasini Sunderraman ,  Han Kung Chua ,  Anil Baby ,  Tin-Cheung Kung ,  Chia-Hung Kuo

IPC分类号： G06F1/32 ,  G06F1/26 ,  G06F13/42 ,  G06F13/38

摘要： Techniques are provided for managing power delivery to multiple universal serial bus (USB) type-C ports of a desktop computer system. In an example, a method can include providing a first power level to a USB power delivery controller during a non-sleep mode operation of the desktop computer, and providing a second power level to the USB power delivery controller when the computer is in a sleep mode, the second power level configured to provide default charge power to a connected device when the computer is in the sleep mode.

公开(公告)号：US09436251B2

公开(公告)日：2016-09-06

申请号：US13996480

申请日：2011-10-01

申请人： Barnes Cooper ,  Faraz A. Siddiqi

发明人： Barnes Cooper ,  Faraz A. Siddiqi

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F9/44 ,  G06F21/81 ,  G06F3/06 ,  G06F12/02 ,  G06F13/00

CPC分类号： G06F1/32 ,  G06F1/3203 ,  G06F1/3275 ,  G06F3/0608 ,  G06F9/4418 ,  G06F12/023 ,  G06F13/00 ,  G06F21/81 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/401 ,  Y02D10/44

摘要： Fast platform hibernation and resumption for computing systems. An embodiment of an apparatus includes a volatile system memory, a nonvolatile memory, and a processor to operate according to an operating system, the processor to transition the apparatus to a first reduced power state upon receipt of a request, the transition to the first reduced power state including the processor to store context information for the computer in the volatile system memory. The apparatus further includes logic to transition the apparatus to a second reduced power state, the logic to copy the context data from the volatile system memory to the nonvolatile memory for the transition to the second reduced power state, where copying of the context data includes the logic to scan the volatile system memory to locate non-active memory elements in the volatile system memory, eliminate the non-active memory elements from the volatile system memory to generate compressed context data, and store the compressed context data in the nonvolatile memory.

摘要翻译： 快速平台休眠和恢复计算系统。 装置的实施例包括易失性系统存储器，非易失性存储器和根据操作系统操作的处理器，所述处理器在接收到请求时将装置转换到第一降低功率状态，转换到第一减少 电源状态包括处理器，用于存储易失性系统存储器中的计算机的上下文信息。 该装置还包括将装置转换到第二降低功率状态的逻辑，将上下文数据从易失性系统存储器复制到非易失性存储器以转换到第二降低功率状态的逻辑，其中上下文数据的复制包括 扫描易失性系统存储器以定位易失性系统存储器中的非活动存储器元件的逻辑，从易失性系统存储器中消除非活动存储器元件以产生压缩上下文数据，并将压缩上下文数据存储在非易失性存储器中。

公开(公告)号：US20150355705A1

公开(公告)日：2015-12-10

申请号：US14298171

申请日：2014-06-06

申请人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

发明人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/0757 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

摘要： In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括多个核心和功率控制器。 功率控制器可以包括硬件占空比（HDC）逻辑，以便即使逻辑处理器具有要执行的工作负载来使得一个核的至少一个逻辑处理器进入强制空闲状态。 此外，如果至少另外一个其他逻辑处理器被阻止进入强制空闲状态，则HDC逻辑可以导致逻辑处理器在空闲周期结束之前退出强制空闲状态。 描述和要求保护其他实施例。

公开(公告)号：US20140223216A1

公开(公告)日：2014-08-07

申请号：US14258921

申请日：2014-04-22

申请人： Barnes Cooper ,  Jaya L. Jeyaseelan ,  Robert E. Gough

发明人： Barnes Cooper ,  Jaya L. Jeyaseelan ,  Robert E. Gough

IPC分类号： G06F1/32

CPC分类号： G06F1/3234 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3253 ,  G06F1/3287 ,  Y02D10/151 ,  Y02D50/20

摘要： A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described.

摘要翻译： 一种用于低功率链路状态智能电源管理的方法和装置。 一些实施例包括用于经由链路耦合到控制器的设备的方法，设备和系统; 链路功率管理引擎，用于基于事务改变链路的功率状态以及对设备和控制器之间的未来事务的一些知识; 以及用于存储链路电源管理引擎的存储器或逻辑。 在一些实施例中，存储器存储关于以下至少一个的信息：链路的功率状态，设备缓冲，控制器或设备状态或事务历史。 在一些实施例中，设备是计算机系统的外设。 在一些实施例中，该方法可以包括将设备转换到各种链路状态。 描述其他实施例。