公开(公告)号：US20110316201A1

公开(公告)日：2011-12-29

申请号：US12822880

申请日：2010-06-24

Applicant: Lin-Chih Huang ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Lin-Chih Huang ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: B06B1/00 ,  H01L21/56 ,  B29C45/07

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L24/94 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: In accordance with an embodiment, a molding apparatus comprises a screen having a planar top surface; a recess in the screen and extending below the planar top surface; a blade capable of traversing the planar top surface; and a molding compound applicator. Another embodiment is a method for molding. The method comprises providing a substrate in a confined volume with an open top surface, applying molding compound in the confined volume, and traversing the open top surface with a blade thereby forming the molding compound to have a planar surface that is co-planar with the open top surface. The substrate has at least one semiconductor die adhered to the substrate.

Abstract translation: 根据实施例，成型设备包括具有平坦顶表面的筛网; 屏幕中的凹槽并在平面顶表面下方延伸; 能够穿过平面顶表面的刀片; 和模塑料涂布器。 另一实施例是一种模制方法。 该方法包括在约束体积中提供具有敞开顶部表面的基底，在约束体积中施加模塑料，并用刀片横穿开放的顶部表面，从而形成模制化合物以具有与该平坦表面共面的平坦表面 开顶表面。 衬底具有至少一个半导体管芯粘附到衬底上。

公开(公告)号：US20110309647A1

公开(公告)日：2011-12-22

申请号：US12818022

申请日：2010-06-17

Applicant: Ku-Feng Yang ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Chen-Hua Yu

Inventor： Ku-Feng Yang ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: B25J15/06 ,  B66C1/02

CPC classification number: H01L21/67346 ,  H01L21/6838 ,  H01L21/68785

Abstract: An apparatus for supporting a wafer includes a base, and a gas-penetration layer. The gas-penetration layer and a portion of the base directly underlying the gas-penetration layer form a gas passage therebetween. The gas passage is configured to be sealed by the wafer placed directly over the gas-penetration layer. The apparatus further includes a valve connected to the gas passage.

Abstract translation: 用于支撑晶片的装置包括基座和气体穿透层。 气体渗透层和直接位于气体穿透层下方的基底的一部分在它们之间形成气体通道。 气体通道被直接设置在气体穿透层上方的晶片密封。 该装置还包括连接到气体通道的阀。

公开(公告)号：US20110266691A1

公开(公告)日：2011-11-03

申请号：US12769251

申请日：2010-04-28

Applicant: Jing-Cheng Lin ,  Ku-Feng Yang

Inventor： Jing-Cheng Lin ,  Ku-Feng Yang

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2224/05552

Abstract: A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.

Abstract translation: 一种器件包括衬底和在衬底上的多个电介质层。 多个金属化层形成在多个电介质层中，其中多个金属化层中的至少一个包括金属焊盘。 贯穿衬底通孔（TSV）从多个电介质层的顶层延伸到衬底的底表面。 深导电通孔从多个电介质层的顶层延伸到金属焊盘上。 金属线形成在多个电介质层的顶层上并且互连TSV和深导电通孔。

公开(公告)号：US20100163842A1

公开(公告)日：2010-07-01

申请号：US12345332

申请日：2008-12-29

Applicant: Li-Shyue Lai ,  Jing-Cheng Lin

Inventor： Li-Shyue Lai ,  Jing-Cheng Lin

IPC: H01L29/15 ,  H01L21/20

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795

Abstract: A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.

Abstract translation: 形成集成电路结构的方法包括：在半导体衬底中形成第一绝缘区域和第二绝缘区域并彼此面对; 以及形成具有反向T形的外延半导体区域。 外延半导体区域包括水平板，该水平板包括在第一绝缘区域和第二绝缘区域之间并邻接第一绝缘区域之间的底部，以及在水平板上并邻接的鳍状物。 水平板的底部接触半导体衬底。 该方法还包括在鳍的顶表面和至少顶部的顶部形成栅电介质; 以及在所述栅极电介质上形成栅电极。

公开(公告)号：US20100065924A1

公开(公告)日：2010-03-18

申请号：US12211464

申请日：2008-09-16

Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/2254 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/49 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device and a method of manufacturing are provided. A substrate has a gate stack formed thereon. Ultra-shallow junctions are formed by depositing an atomic layer of a dopant and performing an anneal to diffuse the dopant into the substrate on opposing sides of the gate stack. The substrate may be recessed prior to forming the atomic layer and the recess may be filled by an epitaxial process. The depositing, annealing, and, if used, epitaxial growth may be repeated a plurality of times to achieve the desired junctions. Source/drain regions are also provided on opposing sides of the gate stack.

Abstract translation: 提供半导体器件和制造方法。 基板上形成有栅叠层。 通过沉积掺杂剂的原子层并执行退火来形成超浅结，以将掺杂剂扩散到栅叠层的相对侧上的衬底中。 衬底可以在形成原子层之前被凹进，并且凹槽可以通过外延工艺填充。 可以重复沉积，退火和（如果使用）外延生长以实现所需的结。 源极/漏极区域也设置在栅极堆叠的相对侧上。

公开(公告)号：US07202162B2

公开(公告)日：2007-04-10

申请号：US10420311

申请日：2003-04-22

Applicant: Jing-Cheng Lin ,  Chao-Hsien Peng ,  Shau Lin Shue ,  Mong Song Liang

Inventor： Jing-Cheng Lin ,  Chao-Hsien Peng ,  Shau Lin Shue ,  Mong Song Liang

IPC: H01L21/4763

CPC classification number: H01L21/76849 ,  H01L21/28562

Abstract: A process for improving the adhesion between an underlying copper structure, and overlying materials and structures, has been developed. The process features formation of a tantalum nitride layer on a copper structure, wherein the copper structure is located in a damascene type opening. To obtain the maximum adhesion benefit the tantalum nitride layer is formed via an atomic deposition layer procedure, performed at specific deposition conditions. The adhesion between the underlying copper structure and overlying materials such as a silicon nitride etch stop layer, as well the adhesion between the lower level copper structure and overlying upper level metal interconnect structures, is improved as a result of the presence of the atomic layer deposited tantalum nitride layer.

Abstract translation: 已经开发了用于改善底层铜结构和上覆材料和结构之间的粘合性的方法。 该方法特征是在铜结构上形成氮化钽层，其中铜结构位于镶嵌型开口中。 为了获得最大的附着效益，通过在特定沉积条件下进行的原子沉积层程序形成氮化钽层。 底层铜结构和上覆材料（例如氮化硅蚀刻停止层）之间的粘附以及下层铜结构和上层金属互连结构之间的粘附性得到改善，原因在于沉积的原子层的存在 氮化钽层。

公开(公告)号：US06969675B2

公开(公告)日：2005-11-29

申请号：US10942355

申请日：2004-09-16

Applicant: Jing-Cheng Lin

Inventor： Jing-Cheng Lin

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

Abstract: It is a general object of the present invention to provide an improved method of fabrication in the formation of an improved copper metal diffusion barrier layer having the structure, W/WSiN/WN, in single and dual damascene interconnect trench/contact via processing with 0.10 micron nodes for MOSFET and CMOS applications. The diffusion barrier is formed by depositing a tungsten nitride bottom layer, followed by an in situ SiH4/NH3 or SiH4/H2 soak forming a WSiN layer, and depositing a final top layer of tungsten. This invention is used to manufacture reliable metal interconnects and contact vias in the fabrication of MOSFET and CMOS devices for both logic and memory applications and the copper diffusion barrier formed, W/WSiN/WN, passes a stringent barrier thermal reliability test at 400° C. Pure single barrier layers, i.e., single layer WN, exhibit copper punch through or copper spiking during the stringent barrier thermal reliability test at 400° C.

Abstract translation: 本发明的一般目的是提供一种改进的制造方法，该方法是在单和双镶嵌互连沟槽/接触通孔加工中具有以下结构的W / WSiN / WN结构的改进的铜金属扩散阻挡层的形成 微米节点用于MOSFET和CMOS应用。 扩散阻挡层是通过沉积氮化钨底层，然后沉积原位SiH 4 / NH 3或SiH 4 H / 浸泡形成WSiN层，并沉积钨的最终顶层。 本发明用于在用于逻辑和存储器应用的MOSFET和CMOS器件的制造中制造可靠的金属互连和接触孔，并且形成的铜扩散阻挡层W / WSiN / WN在400℃下通过严格的阻挡热可靠性测试 在400℃的严格的阻隔热可靠性试验期间，纯单层阻挡层，即单层WN，表现出铜冲穿或铜尖峰。

公开(公告)号：US20050245072A1

公开(公告)日：2005-11-03

申请号：US10833154

申请日：2004-04-28

Applicant: Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

Inventor： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

IPC: H01L21/288 ,  H01L21/4763 ,  H01L21/76 ,  H01L21/768

CPC classification number: H01L21/2885 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76877

Abstract: A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle θ less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.

Abstract translation: 电化学沉积（ECD）的方法在衬底上提供阻挡层和种子层。 在将金属层电化学沉积在具有物理或化学表面处理工艺的电化学镀覆电池中之前，对基板的表面进行预处理。 电化学镀覆电池被盖覆盖以防止电解质溶液的蒸发。 电化学电镀单元包括具有提升密封件的衬底保持器组件，例如在提升密封件和衬底之间的接触角θ小于90°。 衬底保持器组件包括在衬底的后侧的衬底卡盘。

公开(公告)号：US20050097769A1

公开(公告)日：2005-05-12

申请号：US10668291

申请日：2003-09-24

Applicant: Jing-Cheng Lin ,  Shing-Chyang Pan ,  Hsien-Ming Lee ,  Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai ,  Shau-Lin Shue

Inventor： Jing-Cheng Lin ,  Shing-Chyang Pan ,  Hsien-Ming Lee ,  Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai ,  Shau-Lin Shue

IPC: H01L21/677 ,  F26B13/30

CPC classification number: H01L21/67781

Abstract: A loadlock. The loadlock for wafers includes a chamber, a pedestal, a retractable shaft, and a bellows. The chamber has a plurality of walls and a bottom surface. The pedestal supports a cassette and is disposed in the chamber. The retractable shaft has a top end and a bottom end. The top end is connected to the pedestal and the bottom end is connected to the bottom surface as a reference for positioning the pedestal. The bellows has a first end and a second end. The first end is disposed on the pedestal and the second end is sealed at the bottom end of the retractable shaft. Preferably, the retractable shaft is fully enclosed by the bellows.

Abstract translation: 一个加载锁 用于晶片的负荷锁包括一个腔室，一个基座，一个伸缩轴和一个波纹管。 腔室具有多个壁和底面。 基座支撑盒并设置在腔室中。 伸缩轴具有顶端和底端。 顶端连接到基座，底端连接到底面作为基座的基准。 波纹管具有第一端和第二端。 第一端设置在基座上，第二端在可伸缩轴的底端被密封。 优选地，可伸缩轴被波纹管完全包围。

公开(公告)号：US06878615B2

公开(公告)日：2005-04-12

申请号：US09863224

申请日：2001-05-24

Applicant: Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L2221/1063

Abstract: A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

Abstract translation: 公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。 通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。 在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。 所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。