公开(公告)号：US09356096B2

公开(公告)日：2016-05-31

申请号：US14803662

申请日：2015-07-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Song Guo ,  Yushi Hu ,  Roy Meade ,  Sanh D. Tang ,  Michael P. Violette ,  David H. Wells

IPC: H01L29/04 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/32

CPC classification number: H01L29/0649 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76286 ,  H01L29/04 ,  H01L29/32

Abstract: Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size of the contact area on a substrate at which growth begins. During growth, the epitaxial material grows vertically from the contact area and laterally over the projection. The projection provides a stress relaxation region for the lateral growth to reduce dislocation and stacking faults at the side edges of the grown epitaxial material.

公开(公告)号：US20160111639A1

公开(公告)日：2016-04-21

申请号：US14515998

申请日：2014-10-16

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Christopher D. Cardon ,  Caner Onal

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L27/2427 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/33 ,  G11C2213/35 ,  G11C2213/52 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1608

Abstract: The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device.

Abstract translation: 本公开包括使用用于存储器单元应用的选择装置的选择装置和方法。 示例性选择装置包括具有特定几何形状的第一电极，形成在第一电极上的半导体材料和形成在半导体材料上的具有特定几何形状的第二电极，其中所述选择装置被配置为响应于 施加到选择设备的信号。

公开(公告)号：US09269899B1

公开(公告)日：2016-02-23

申请号：US14615188

申请日：2015-02-05

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Marko Milojevic ,  David H. Wells ,  F. Daniel Gealy

IPC: G11C5/12 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L45/126 ,  G11C5/12 ,  G11C11/221 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/76 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: An electronic device includes two conductive electrodes. A first current path extends from one of the electrodes to the other and has a dominant thermally activated conduction activation energy of 0.5 eV to 3.0 eV. A second current path extends from the one electrode to the other and is circuit-parallel the first current path. The second current path exhibits a minimum 100-times increase in electrical conductivity for increasing temperature within a temperature range of no more than 50° C. between 300° C. and 800° C. and exhibits a minimum 100-times decrease in electrical conductivity for decreasing temperature within the 50° C. temperature range. Other embodiments are disclosed.

Abstract translation: 电子设备包括两个导电电极。 第一电流路径从一个电极延伸到另一个电极，并且具有0.5eV至3.0eV的显性热激活传导激活能。 第二电流路径从一个电极延伸到另一个电极并且与第一电流路径电路并联。 在300℃和800℃之间，在不超过50℃的温度范围内增加温度，第二电流路径的电导率最小提高100倍，并且电导率最小降低100倍 用于在50°C温度范围内降低温度。 公开了其他实施例。

公开(公告)号：US20150206761A1

公开(公告)日：2015-07-23

申请号：US14676338

申请日：2015-04-01

Applicant: Micron Technology, Inc.

Inventor： Janos Fucsko ,  David H. Wells ,  Patrick M. Flynn ,  Whonchee Lee

IPC: H01L21/306 ,  H01L21/302 ,  H01L21/311

CPC classification number: H01L21/30608 ,  H01L21/302 ,  H01L21/31116 ,  H01L21/76232 ,  H01L29/66818

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.

Abstract translation: 单晶硅蚀刻方法包括提供其中具有至少一个沟槽的单晶硅衬底。 将单晶硅衬底暴露于底切单晶硅的各向异性蚀刻剂。 通过控制蚀刻的长度，可以产生单晶硅中的单晶硅岛或平滑的垂直壁。

公开(公告)号：US12185549B2

公开(公告)日：2024-12-31

申请号：US18209204

申请日：2023-06-13

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  David H. Wells ,  Umberto Maria Meotto

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27 ,  H10B43/50

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.

公开(公告)号：US20240284672A1

公开(公告)日：2024-08-22

申请号：US18443013

申请日：2024-02-15

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Matthew J. King ,  Indra V. Chary ,  Yoshiaki Fukuzumi ,  Lifang Xu ,  Paolo Tessariol ,  Shuangqiang Luo

IPC: H10B43/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B43/10

Abstract: Methods, systems, and devices for merged cavities for conductor formation in a memory die are described. An array of cavities may be formed through a stack of material layers of a memory die, and conductors may be formed at least in part by merging some of the cavities of the array. Such cavities may be sized in accordance with a relatively smallest feature that implements a subset of such cavities, and a smallest associated feature may be formed using a first subset of the array of cavities. Conductors may be formed at least in part by merging two or more cavities of a second subset of the array of cavities using a material removal operation to remove portions of the stack of material layers. Such merging may support conductors being formed with a cross-section that is greater than a cross-section of other features formed using such cavities that are not merged.

公开(公告)号：US20240074177A1

公开(公告)日：2024-02-29

申请号：US17822101

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Justin D. Shepherdson ,  Swapnil A. Lengade ,  Collin Howder ,  Dheeraj Kumar ,  Andrew L. Li

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: Microelectronic devices include a region with a tiered stack that includes insulative, conductive, and non-conductive structures arranged in tiers. The insulative structures vertically alternate with both the conductive and the non-conductive structures. Each of the conductive structures is vertically spaced from another of the conductive structures by at least one of the non-conductive structures and at least two of the insulative structures. A composition of the non-conductive structures differs from a composition of the insulative structures. In methods of fabrication, a precursor stack is formed to include the insulative structures vertically alternating with first and second non-conductive structures. In a region of the precursor stack, the first non-conductive structures are removed, forming voids between multi-structure tier groups. Conductive structures are formed in the voids. Electronic systems are also disclosed.

公开(公告)号：US20230395422A1

公开(公告)日：2023-12-07

申请号：US17863317

申请日：2022-07-12

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  David H. Wells ,  Byeung Chul Kim ,  Richard H. Hill ,  Paolo Tessariol

IPC: H01L21/762 ,  G11C16/04 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L21/76232 ,  G11C16/0483 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11519

Abstract: Methods, systems, and devices for selective cavity merging for isolation regions in a memory die are described. For example, formation of material structures of a memory die may include depositing a stack of alternating layers of a first material and a second material over a substrate of the memory die, forming a pattern of cavities through the stack of alternating material layers, and forming voids between layers of the first material based on removing portions of the second material. An electrical isolation region may be formed between portions of the memory die based on depositing a dielectric material in at least some of the cavities and in at least a portion of the voids between the layers of the first material.

公开(公告)号：US20230309426A1

公开(公告)日：2023-09-28

申请号：US17656280

申请日：2022-03-24

Applicant: Micron Technology, Inc.

Inventor： Stephen W. Russell ,  Enrico Varesi ,  David H. Wells ,  Paolo Fantini ,  Lorenzo Fratin

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  G11C13/0028 ,  H01L27/2481 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/1608

Abstract: Methods, systems, and devices for sparse piers for three-dimensional memory arrays are described. A semiconductor device, such as a memory die, may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide mechanical support for subsequent processing. For example, a memory die may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. In some examples, the alternating layers may be formed into one or more pairs of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns to provide mechanical support between instances of the cross-sectional patterns, or between layers of the cross-sectional patterns (e.g., when one or more layers are removed from the cross-sectional patterns), or both.

公开(公告)号：US20230009880A1

公开(公告)日：2023-01-12

申请号：US17373121

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  David H. Wells ,  Harsh Narendrakumar Jain ,  Umberto Maria Meotto ,  Paolo Tessariol

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

Abstract: Integrated circuitry comprises two three-dimensional (3D) array regions individually comprising tiers of electronic components. A stair-step region is between the two 3D-array regions. First stair-step structures alternate with second stair-step structures along a first direction within the stair-step region. The first stair-step structures individually comprise two opposing first flights of stairs in a first vertical cross-section along the first direction. The stairs in the first flights each have multiple different-depth treads in a second vertical cross-section that is along a second direction that is orthogonal to the first direction. The second stair-step structures individually comprise two opposing second flights of stairs in the first vertical cross-section. The stairs in the second flights each have only a single one tread along the second direction. Other embodiments, including method, are disclosed.