公开(公告)号：US09147485B2

公开(公告)日：2015-09-29

申请号：US13871891

申请日：2013-04-26

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Chi Lo

IPC: G11C7/10 ,  G11C16/28 ,  G11C16/04 ,  G11C16/06 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C11/56 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/28 ,  Y10T29/49117

Abstract: Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement.

Abstract translation: 各种实施例解决了诸如3D垂直门闪存和多电平单元存储器的各种存储器架构中的源侧感测困难的各种困难。 一个这样的困难是，通过源侧感测，信号幅度显着小于漏极侧感测。 另一个这样的困难是与多电平单元存储器相关联的噪声和降低的感测裕度。 在一些实施例中，位线在施加读取偏置布置之前被选择性地放电。

公开(公告)号：US09146809B2

公开(公告)日：2015-09-29

申请号：US14047418

申请日：2013-10-07

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Chang Huang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1052 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an ECC and an extended bit derived from the ECC. The method includes overwriting the extended ECC with a pre-determined state during a second program operation to indicate the second program operation. The method includes, setting the ECC to an initial ECC state before the first program operation; during the first program operation, computing the ECC, changing the ECC to the initial ECC state if the computed ECC equals the pre-determined state; and changing the extended bit to an initial value if the ECC equals the initial ECC state. The method includes reading an extended ECC including an extended bit and an ECC for corresponding data, and determining whether to enable ECC logic using the extended ECC.

Abstract translation: 提供一种操作存储用于相应数据的ECC的存储设备的方法。 该方法包括在第一程序操作期间写入扩展ECC，扩展ECC包括ECC和从ECC导出的扩展位。 该方法包括在第二程序操作期间以预定状态重写扩展ECC以指示第二程序操作。 该方法包括：在第一程序操作之前将ECC设置为初始ECC状态; 在第一程序操作期间，如果所计算的ECC等于预定状态，则计算ECC，将ECC改变为初始ECC状态; 并且如果ECC等于初始ECC状态，则将扩展位改变为初始值。 该方法包括读取包括扩展位的扩展ECC和用于相应数据的ECC，并且确定是否使用扩展ECC来启用ECC逻辑。

公开(公告)号：US09093172B2

公开(公告)日：2015-07-28

申请号：US14249270

申请日：2014-04-09

Applicant: Macronix International Co., Ltd.

Inventor： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

IPC: G11C11/34 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/14

CPC classification number: G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

Abstract: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.

Abstract translation: 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。 该设备还包括用于从存储设备外部的源接收命令的命令接口。 该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。 泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

公开(公告)号：US20140361824A1

公开(公告)日：2014-12-11

申请号：US14467419

申请日：2014-08-25

Applicant: Macronix International Co., Ltd.

Inventor： Chung-Kuang Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen

IPC: H03K19/0175 ,  G05F3/02

CPC classification number: H03K19/018528 ,  G05F3/02 ,  G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  G06F1/12 ,  H03K19/0175 ,  H03L5/00

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract translation: 集成电路的时钟电路具有诸如温度，接地噪声和功率噪声的变化。 改进的时钟集成电路的各个方面解决了温度，地面噪声和功率噪声中的一个或多个变化。

公开(公告)号：US20140269127A1

公开(公告)日：2014-09-18

申请号：US13854548

申请日：2013-04-01

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Han Sung Chen ,  Ming Chao Lin

IPC: G11C7/08

CPC classification number: G11C7/22 ,  G11C5/145 ,  G11C8/08 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2272 ,  G11C2207/2281

Abstract: An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.

Abstract translation: 具有存储器的集成电路可以在诸如读取操作的连续操作之间以较低的延迟进行操作。 第一次，在集成电路上的存储器阵列上完成第一操作命令。 第二次，在存储器阵列上开始第二操作命令。 来自电荷泵的稳定的输出电压被耦合到存储器阵列中的字线。 从第一次到第二次，稳定的输出电压保持在诸如读取电压的字线操作电压。

公开(公告)号：US20140258794A1

公开(公告)日：2014-09-11

申请号：US14055656

申请日：2013-10-16

Applicant: Macronix International Co., Ltd.

Inventor： Yih-Shan Yang ,  Shou-Nan Hung ,  Chun-Hsiung Hung ,  Yao-Jen Kuo ,  Meng-Fan Chang

IPC: G06F11/07

CPC classification number: G06F11/076 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679 ,  G06F11/0727 ,  G06F11/0787 ,  G06F11/08 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/00 ,  G11C29/022 ,  G11C29/42 ,  G11C29/44 ,  G11C2216/14

Abstract: Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes.

Abstract translation: 计数状态电路电耦合到相应的状态元件。 状态元件可选地存储耦合到存储器阵列的位线的位状态。 位状态可以指示至少通过和失败。 计数状态电路按顺序相互电耦合。 控制逻辑使得按顺序处理计数状态电路以确定存储位状态的存储元件的总数。 存储位状态的存储元件的总数表示错误位数或非错误位的数量，这可以帮助确定错误纠正码是否存在太多的错误。

公开(公告)号：US20140254284A1

公开(公告)日：2014-09-11

申请号：US14046428

申请日：2013-10-04

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Ti Wen Chen ,  Shuo-Nan Hung ,  Shih-Lin Huang

IPC: G11C16/16

CPC classification number: G11C16/16 ,  G11C16/08 ,  G11C16/12

Abstract: A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage. In a second mode, the first transistor decouples the word line from the global word line, and the second transistor couples the word line to the ground voltage.

Abstract translation: 存储器电路包括耦合到存储器阵列的字线，包括在擦除操作中取消选择的一个或多个字线的第一组以及在擦除操作中选择的一个或多个字线的第二组。 响应于接收到擦除操作的擦除命令，控制电路将擦除操作中未选择的一个或多个字线的第一组耦合到参考电压。 一些示例还包括可将字线可切换地耦合到全局字线的第一晶体管，以及可切换地将字线耦合到接地电压的第二晶体管。 控制电路耦合到第一晶体管和第二晶体管，其中控制电路具有包括至少擦除操作的多个模式。 在第一模式中，第一晶体管将字线耦合到全局字线，并且第二晶体管将字线与接地电压分离。 在第二模式中，第一晶体管将字线与全局字线分离，并且第二晶体管将字线耦合到接地电压。

公开(公告)号：US20140146611A1

公开(公告)日：2014-05-29

申请号：US13688623

申请日：2012-11-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

IPC: G11C16/30

CPC classification number: G11C16/30 ,  G11C11/5628 ,  G11C16/24 ,  G11C16/34 ,  G11C16/3427 ,  G11C16/3436 ,  G11C16/3454

Abstract: A method for programming a memory cell of a memory device includes the following steps. A plurality of cycle number ranges are set up. A specific one of the plurality of cycle number ranges, in which the memory cell having a drain terminal passes a program-verification, is determined. A bias voltage is applied to the drain terminal for programming the memory cell, wherein the bias voltage varies with the specific cycle number range.

Abstract translation: 一种用于编程存储器件的存储器单元的方法包括以下步骤。 设置多个循环数范围。 确定具有漏极端子的存储单元通过程序验证的多个循环数范围中的特定的一个。 向漏极端子施加偏置电压以对存储器单元进行编程，其中偏置电压随特定周期数范围变化。

公开(公告)号：US20240311014A1

公开(公告)日：2024-09-19

申请号：US18524337

申请日：2023-11-30

Applicant: Macronix International Co., Ltd.

Inventor： Wu-Chin Peng ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

Abstract: Systems, devices, methods, and circuits for managing read timing in semiconductor devices are provided. In one aspect, a semiconductor device includes: a memory array configured to store data and a circuitry coupled to the memory array and configured to read stored data from the memory array. The circuitry is configured to: obtain a starting address of target data to be read based on a read instruction, determine that the starting address is in a first address group of a plurality of address groups, each of the plurality of address groups being associated with a respective reading speed, and read out the target data from the memory array based on the starting address being in the first address group.

公开(公告)号：US20240118806A1

公开(公告)日：2024-04-11

申请号：US17961176

申请日：2022-10-06

Applicant: Macronix International Co., Ltd.

Inventor： Chin-Hung Chang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679

Abstract: Systems, devices, methods, and circuits for managing content addressable memory (CAM) devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in memory cells, and a circuitry coupled to the memory cell array and configured to execute a search operation in the memory cell array according to a search instruction. The search instruction includes at least one of search data or an option code, and the option code specifies, for the search operation, at least one of a search length or a search depth.