公开(公告)号：US20180003761A1

公开(公告)日：2018-01-04

申请号：US15387370

申请日：2016-12-21

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Enrico Castaldo ,  Raul Andres Bianchi ,  Francesco La Rosa

IPC: G01R31/02 ,  G01R31/28

CPC classification number: G01R31/028 ,  G01R31/2882 ,  G04F10/10

Abstract: A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.

公开(公告)号：US20170302168A1

公开(公告)日：2017-10-19

申请号：US15363631

申请日：2016-11-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Paola Cavaleri

IPC: H02M3/07

CPC classification number: H02M3/07 ,  G11C5/145 ,  G11C16/30

Abstract: A charge pump circuit can be controlled by a control signal that is generated from a first signal coming from and output signal of the charge pump circuit, from a reference signal, and from a clock signal. The generation of the control signal includes a comparison of the reference signal and of the first signal in tempo with a timing signal coming from the clock signal.

公开(公告)号：US09666484B2

公开(公告)日：2017-05-30

申请号：US14806432

申请日：2015-07-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud Regnier ,  Stephan Niel ,  Francesco La Rosa

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/265 ,  H01L27/108 ,  H01L27/1157 ,  H01L29/772 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11524 ,  H01L27/11556

CPC classification number: H01L21/823468 ,  H01L21/26513 ,  H01L21/28273 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4236 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/66613 ,  H01L29/66825 ,  H01L29/772 ,  H01L29/7881

Abstract: An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor gate structure, a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor, and a first spacer formed on the first edge of the gate structure and above the first doped region. The first spacer completely covers the first doped region and a silicide is present on the trench conductor but is not present on the surface of the first doped region.

公开(公告)号：US20170117326A1

公开(公告)日：2017-04-27

申请号：US15398228

申请日：2017-01-04

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L27/24 ,  H01L29/66 ,  H01L45/00 ,  H01L29/732

CPC classification number: H01L27/2445 ,  H01L27/226 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732 ,  H01L45/04 ,  H01L45/06 ,  H01L45/16

Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.

公开(公告)号：US20170084336A1

公开(公告)日：2017-03-23

申请号：US15365367

申请日：2016-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G11C16/08 ,  G11C16/26 ,  G11C16/14

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

Abstract: The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the first row of memory cells, and a second driver coupled to a control line of the second row of memory cells. The first driver is made in a first well, the second driver is made in a second well electrically insulated from the first well, and the two rows of memory cells are produced in a memory array well electrically insulated from the first and second wells.

公开(公告)号：US09543311B2

公开(公告)日：2017-01-10

申请号：US14625356

申请日：2015-02-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  G11C16/14 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L21/266 ,  H01L21/3213

CPC classification number: H01L29/7883 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/788

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

Abstract translation: 各种实施例提供了一种存储单元，其包括垂直选择栅极，在衬底上方延伸的浮置栅极，其中浮置栅极还在非零重叠距离上延伸在垂直选择栅极的一部分上方，存储器单元包括掺杂 注入在与选择栅极相对延伸的垂直沟道区域和与浮动栅极相对延伸的水平沟道区域的交点处的区域。

公开(公告)号：US20160372561A1

公开(公告)日：2016-12-22

申请号：US15252090

申请日：2016-08-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud Regnier ,  Jean-Michel Mirabel ,  Stephan Niel ,  Francesco La Rosa

IPC: H01L29/423 ,  H01L27/115 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L29/42336 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/7889

Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.

Abstract translation: 形成在半导体衬底中的存储单元包括在衬底中形成的沟槽中垂直延伸的选择栅极，并且通过栅极氧化物的第一层与衬底隔离，水平浮动栅极延伸在衬底上方并与衬底隔离，并与衬底隔离 栅极氧化物的第二层和在浮置栅极上方延伸的水平控制栅极。 选择栅极覆盖浮动栅极的侧面。 浮置栅极仅由第一层栅极氧化物与选择栅极分离，并且与垂直沟道区分离，仅沿着选择栅极在衬底中延伸，仅由栅极氧化物的第二层分离。

公开(公告)号：US09460798B2

公开(公告)日：2016-10-04

申请号：US14795742

申请日：2015-07-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G11C16/04 ,  G11C16/14 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

Abstract: A non-volatile memory includes bit lines, a first page-erasable sector including memory cells of a first type, and a second word-erasable or bit-erasable sector including memory cells of a second type. The memory cells of the first type comprise a single floating-gate transistor and the memory cells of the second type comprise a first floating-gate transistor and a second floating-gate transistor the floating gates of which are electrically coupled, the second floating-gate transistor of a memory cell of the second type enabling the memory cell to be individually erased.

Abstract translation: 非易失性存储器包括位线，包括第一类型的存储器单元的第一可寻址扇区和包括第二类型的存储单元的第二可擦除或可位可擦除扇区。 第一类型的存储单元包括单个浮栅晶体管，并且第二类型的存储单元包括第一浮栅晶体管和浮置栅电耦合的第二浮栅晶体管，第二浮栅 第二种类型的存储器单元的晶体管使得能够单独地擦除存储单元。

公开(公告)号：US09406686B2

公开(公告)日：2016-08-02

申请号：US14528785

申请日：2014-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Julien Delalleau ,  Arnaud Regnier

IPC: H01L27/115 ,  H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  G11C16/14 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/78 ,  G11C16/04

CPC classification number: H01L29/42328 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

Abstract translation: 本公开涉及一种存储单元，其包括在衬底中形成的沟槽中延伸的垂直选择栅极，在衬底上方延伸的浮动栅极以及在浮置栅极上方延伸的水平控制栅极，其中浮动栅极还在部分 的垂直选择门在非零重叠距离上。 主要用于生产通过热电子注入可编程的分离栅极存储单元。

公开(公告)号：US20160071598A1

公开(公告)日：2016-03-10

申请号：US14810283

申请日：2015-07-27

Applicant: STMicroelectronics ( Rousset ) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

Abstract: A method controls a memory that includes twin memory cells formed in a semiconductor substrate. Each memory cell includes a floating-gate transistor including a state control gate, in series with a select transistor that includes a vertical select control gate, common to the twin memory cells, and a source connected to an embedded source line, common to the memory cells. The drains of the floating-gate transistors of the twin memory cells are connected to a same bit line. The method includes controlling a memory cell so as to turn it on to couple the source line to a bit line coupled to the ground, during a step of programming or reading another memory cell.

Abstract translation: 一种方法控制包括形成在半导体衬底中的双存储单元的存储器。 每个存储单元包括一个浮动栅极晶体管，它包括状态控制栅极，与选择晶体管串联，该选择​​晶体管包括双存储单元共用的垂直选择控制栅极和连接到存储器共用的嵌入式源极线路的源极 细胞。 双存储单元的浮栅晶体管的漏极连接到相同的位线。 该方法包括在编程或读取另一个存储器单元的步骤期间控制存储器单元以将其导通以将源极线耦合到耦合到地的位线。