公开(公告)号：US20240145257A1

公开(公告)日：2024-05-02

申请号：US18410365

申请日：2024-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tin-Hao Kuo

IPC: H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L21/565 ,  H01L21/76802 ,  H01L23/3121 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/0231 ,  H01L2224/02375 ,  H01L2224/02381

Abstract: A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer.

公开(公告)号：US11848319B2

公开(公告)日：2023-12-19

申请号：US17883878

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Kuo Lung Pan ,  Hung-Yi Kuo ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/24 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L25/18 ,  H01L23/24 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L25/50 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3135 ,  H01L24/20 ,  H01L2224/02311 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/06155 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13024 ,  H01L2224/24101 ,  H01L2224/24147 ,  H01L2224/32147 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2924/14 ,  H01L2924/181

Abstract: A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.

公开(公告)号：US11764171B2

公开(公告)日：2023-09-19

申请号：US17241715

申请日：2021-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo Lung Pan ,  Tin-Hao Kuo ,  Hao-Yi Tsai

IPC: H01L23/64 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/645 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/1437 ,  H01L2924/1903 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

公开(公告)号：US20230253358A1

公开(公告)日：2023-08-10

申请号：US18302935

申请日：2023-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Yu Wu ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/498 ,  H05K1/11 ,  H01L25/10 ,  H01L29/66 ,  H01L25/065 ,  H01L23/528

CPC classification number: H01L24/17 ,  H01L23/528 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/09 ,  H01L24/14 ,  H01L24/16 ,  H01L24/33 ,  H01L24/81 ,  H01L25/105 ,  H01L25/0657 ,  H01L29/66 ,  H05K1/111 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0235 ,  H01L2224/0401 ,  H01L2224/1308 ,  H01L2224/02375 ,  H01L2224/3003 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14133 ,  H01L2224/16013 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2225/1047 ,  H01L2924/3512 ,  H01L2924/3841 ,  H01L2924/35121 ,  H05K2201/09727 ,  H05K2201/10674

Abstract: A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of the first package component. The second metal trace is parallel to the first metal trace. The second metal trace includes a narrow metal trace portion having a first width, and a wide metal trace portion having a second width greater than the first width connected to the narrow metal trace portion. The second package component is over the first package component. The second package component includes a metal bump overlapping a portion of the first metal trace, and a conductive connection bonding the metal bump to the first metal trace. The conductive connection contacts a top surface and sidewalls of the first metal trace. The metal bump is neighboring the narrow metal trace portion.

公开(公告)号：US20230123427A1

公开(公告)日：2023-04-20

申请号：US18068010

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48

Abstract: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.

公开(公告)号：US11444002B2

公开(公告)日：2022-09-13

申请号：US16941541

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hsiao-Chung Liang ,  Hao-Yi Tsai ,  Chien-Ling Hwang ,  Kuo-Lung Pan ,  Pei-Hsuan Lee ,  Tin-Hao Kuo ,  Chih-Hsuan Tai

IPC: H01L23/40 ,  H01L23/58 ,  H01L25/18 ,  H01L23/00

Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.

公开(公告)号：US20220223572A1

公开(公告)日：2022-07-14

申请号：US17657843

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tin-Hao Kuo

IPC: H01L25/10 ,  H01L25/18 ,  H01L25/00

Abstract: A package includes a building block. The building block includes a device die, an interposer bonded with the device die, and a first encapsulant encapsulating the device die therein. The package further includes a second encapsulant encapsulating the building block therein, and an interconnect structure over the second encapsulant. The interconnect structure has redistribution lines electrically coupling to the device die. A power module is over the interconnect structure. The power module is electrically coupled to the building block through the interconnect structure.

公开(公告)号：US11289373B2

公开(公告)日：2022-03-29

申请号：US16504328

申请日：2019-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Bor-Rung Su ,  De-Yuan Lu ,  Hao-Yi Tsai ,  Tin-Hao Kuo ,  Tzung-Hui Lee ,  Tai-Min Chang

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/027 ,  H01L21/56

Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.

公开(公告)号：US20220037228A1

公开(公告)日：2022-02-03

申请号：US16941541

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hsiao-Chung Liang ,  Hao-Yi Tsai ,  Chien-Ling Hwang ,  Kuo-Lung Pan ,  Pei-Hsuan Lee ,  Tin-Hao Kuo ,  Chih-Hsuan Tai

IPC: H01L23/40 ,  H01L23/58 ,  H01L25/18 ,  H01L23/00

Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.

公开(公告)号：US20220013422A1

公开(公告)日：2022-01-13

申请号：US16924208

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Yen Chang ,  Chih-Wei Lin ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Chun-Cheng Lin ,  Tin-Hao Kuo ,  Yu-Chia Lai ,  Chih-Hsuan Tai

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/40 ,  H01L23/538 ,  H01L23/498 ,  H01L25/00

Abstract: Provided is a package structure including a composite wafer, a plurality of dies, an underfill, and a plurality of dam structures. The composite wafer has a first surface and a second surface opposite to each other. The composite wafer includes a plurality of seal rings dividing the composite wafer into a plurality of packages; and a plurality of through holes respectively disposed between the seal rings and penetrating through the first and second surfaces. The dies are respectively bonded onto the packages at the first surface by a plurality of connectors. The underfill laterally encapsulates the connectors. The dam structures are disposed on the first surface of the composite wafer to separate the underfill from the through holes.