公开(公告)号：US20160099174A1

公开(公告)日：2016-04-07

申请号：US14504067

申请日：2014-10-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yung-Hsu Wu ,  Cheng- Hsiung Tsai ,  Yu-Sheng Chang ,  Chia-Tien Wu ,  Chung-Ju Lee ,  Yung-Sung Yen ,  Chun-Kuang Chen ,  Tien-I Bao ,  Ru-Gun Liu ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/311

CPC分类号： H01L21/76877 ,  H01L21/02115 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L23/5283 ,  H01L2221/1063

摘要： Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate. A via pattern including a plurality of openings may be defined above the substrate. A spacer material layer is formed on a sidewall at least one trench. Via holes can be etched in the dielectric layer using the via pattern and spacer material layer as a masking element.

摘要翻译： 提供了半导体器件制造方法，其包括提供具有设置在形成在衬底上方的电介质层中的多个沟槽的衬底的方法。 可以在衬底上限定包括多个开口的通孔图案。 在侧壁上形成间隔材料层至少一个沟槽。 可以使用通孔图案和间隔材料层作为掩模元件在电介质层中蚀刻通孔。

公开(公告)号：US20160079063A1

公开(公告)日：2016-03-17

申请号：US14937366

申请日：2015-11-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Ju Lee ,  Hsin-Chieh Yao ,  Shau-Lin Shue ,  Tien-I Bao ,  Yung-Hsu Wu

IPC分类号： H01L21/033 ,  H01L21/768

CPC分类号： H01L21/0274 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76879 ,  H01L2224/29575 ,  H01L2224/37572 ,  H01L2225/1058

摘要： A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the third mandrel being between the first mandrel and the second mandrel, and etching the third mandrel to cut the third mandrel into a fourth mandrel and a fifth mandrel, with an opening separating the fourth mandrel from the fifth mandrel. A spacer layer is formed on sidewalls of the first, the second, the fourth, and the fifth mandrels, wherein the opening is fully filled by the spacer layer. Horizontal portions of the spacer layer are removed, with vertical portions of the spacer layer remaining un-removed. A target layer is etched using the first, the second, the fourth, and the fifth mandrels and the vertical portions of the spacer layer as an etching mask, with trenches formed in the target layer. The trenches are filled with a filling material.

摘要翻译： 一种方法包括执行双重图案化处理以形成第一心轴，第二心轴和第三心轴，其中第三心轴位于第一心轴和第二心轴之间，并且蚀刻第三心轴以将第三心轴切割成第四心轴 心轴和第五心轴，具有将第四心轴与第五心轴分开的开口。 间隔层形成在第一，第二，第四和第五心轴的侧壁上，其中开口被间隔层完全填充。 间隔层的水平部分被去除，间隔层的垂直部分保持未被去除。 使用第一，第二，第四和第五心轴以及间隔层的垂直部分作为蚀刻掩模蚀刻靶层，其中在目标层中形成沟槽。 沟槽填充有填充材料。

公开(公告)号：US09252049B2

公开(公告)日：2016-02-02

申请号：US13787492

申请日：2013-03-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Hsien Peng ,  Tsung-Min Huang ,  Hsiang-Huan Lee ,  Shau-Lin Shue

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/32133 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features.

摘要翻译： 形成互连结构的方法包括在半导体衬底上形成电介质材料层。 图案化电介质材料层以在其中形成多个通孔。 第一金属层形成在电介质材料层上，其中第一金属层填充多个通孔。 第一金属层被平坦化，使得其顶部与电介质材料层的顶部共面，以形成多个第一金属特征。 在多个第一金属特征中的每一个的顶部上形成停止层，其中，停止层停止随后的蚀刻以蚀刻到多个第一金属特征中。

公开(公告)号：US09230911B2

公开(公告)日：2016-01-05

申请号：US14144245

申请日：2013-12-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Hai-Ching Chen ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L21/4763 ,  H01L29/40 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/498 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5222 ,  H01L23/53204 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature and a second conductive feature in the LK dielectric layer; a first spacer along a first sidewall of the first conductive feature; a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature; an air gap between the first spacer and the second spacer; and a third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature.

摘要翻译： 公开了互连结构和形成互连结构的方法。 互连结构包括在衬底上的低k（LK）电介质层; LK介电层中的第一导电特征和第二导电特征; 沿所述第一导电特征的第一侧壁的第一间隔物; 沿着第二导电特征的第二侧壁的第二间隔物，其中第二导电特征的第二侧壁面向第一导电特征的第一侧壁; 第一间隔件和第二间隔件之间的气隙; 以及在所述第一导电特征上的第三导电特征，其中所述第三导电特征连接到所述第一导电特征。

公开(公告)号：US20150340239A1

公开(公告)日：2015-11-26

申请号：US14816946

申请日：2015-08-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Shau-Lin Shue

IPC分类号： H01L21/308

CPC分类号： H01L21/0338 ,  B29C33/38 ,  B29L2031/757 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116

摘要： Disclosed herein is a method of forming a structure, comprising forming a mandrel layer over a substrate, masking the mandrel layer with a first mask and performing a first etch on the mandrel layer, the first etch forming a first opening exposing a first portion of the substrate. The mandrel layer is masked with a second mask and a second etch is performed on the mandrel layer. The second etch forms a second opening exposing a second portion of the substrate, and also forms a protective layer on the first portion of the substrate and in the first opening.

公开(公告)号：US09142509B2

公开(公告)日：2015-09-22

申请号：US14332866

申请日：2014-07-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chen-Hua Yu ,  Shau-Lin Shue ,  Hsiang-Huan Lee ,  Ching-Fu Yeh

IPC分类号： H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76858 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/53271 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A copper interconnect structure in a semiconductor device comprises a dielectric layer having sidewalls and a surface defining an opening in the dielectric layer. The copper interconnect structure also comprises a barrier layer deposited on the sidewalls and the surface of the dielectric layer defining the opening. The copper interconnect structure further comprises a barrier/seed mixed layer deposited on the barrier layer. The copper interconnect structure additionally comprises an adhesive layer deposited on the barrier/seed mixed layer. The copper interconnect structure also comprises a seed layer deposited on the adhesive layer.

摘要翻译： 半导体器件中的铜互连结构包括具有侧壁和在电介质层中限定开口的表面的电介质层。 铜互连结构还包括沉积在限定开口的侧壁和介电层的表面上的阻挡层。 铜互连结构还包括沉积在阻挡层上的阻挡/种子混合层。 铜互连结构还包括沉积在阻挡/种子混合层上的粘合剂层。 铜互连结构还包括沉积在粘合剂层上的种子层。

公开(公告)号：US09136106B2

公开(公告)日：2015-09-15

申请号：US14134027

申请日：2013-12-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chieh-Han Wu ,  Chung-Ju Lee ,  Cheng-Hsiung Tsai ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L21/00 ,  H01L21/46 ,  H01L21/02 ,  H01L21/027 ,  H01L21/308

CPC分类号： H01L21/76816 ,  H01L21/02104 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802

摘要： A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.

摘要翻译： 形成目标图案的方法包括在第一掩模上在衬底上形成多条线，并在该衬底上，多条线上以及多条线的侧壁上形成第一间隔层。 多条线被去除，从而在衬底上提供图案化的第一间隔层。 所述方法还包括在所述图案化的第一间隔层上以及所述图案化的第一间隔层的侧壁上方在所述衬底上形成第二间隔层，以及在所述第二间隔层上形成具有第二掩模的图案化材料层。 由此，图案化材料层和第二间隔层共同限定多个沟槽。

公开(公告)号：US20150187696A1

公开(公告)日：2015-07-02

申请号：US14144245

申请日：2013-12-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Hai-Ching Chen ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/528 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5222 ,  H01L23/53204 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature and a second conductive feature in the LK dielectric layer; a first spacer along a first sidewall of the first conductive feature; a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature; an air gap between the first spacer and the second spacer; and a third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature.

摘要翻译： 公开了互连结构和形成互连结构的方法。 互连结构包括在衬底上的低k（LK）电介质层; LK介电层中的第一导电特征和第二导电特征; 沿所述第一导电特征的第一侧壁的第一间隔物; 沿着第二导电特征的第二侧壁的第二间隔物，其中第二导电特征的第二侧壁面向第一导电特征的第一侧壁; 第一间隔件和第二间隔件之间的气隙; 以及在所述第一导电特征上的第三导电特征，其中所述第三导电特征连接到所述第一导电特征。

公开(公告)号：US20150155198A1

公开(公告)日：2015-06-04

申请号：US14096963

申请日：2013-12-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsiung Tsai ,  Yung-Hsu Wu ,  Tsung-Min Huang ,  Chung-Ju Lee ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/3213

CPC分类号： H01L21/76877 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3085 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76816

摘要： Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask.

公开(公告)号：US20150155171A1

公开(公告)日：2015-06-04

申请号：US14096864

申请日：2013-12-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Sheng Chang ,  Chung-Ju Lee ,  Cheng-Hsiung Tsai ,  Yung-Hsu Wu ,  Hsiang-Huan Lee ,  Hai-Ching Chen ,  Ming-Feng Shieh ,  Tien-I Bao ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Shau-Lin Shue

IPC分类号： H01L21/033

CPC分类号： H01L21/0338 ,  H01L21/02186 ,  H01L21/02282 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/32139

摘要： A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

摘要翻译： 用于图案化半导体器件的方法实施例包括在硬掩模上构图虚拟层以形成一个或多个虚拟线。 侧壁对齐的间隔件在一个或多个虚线和硬掩模上顺应地形成。 第一反向材料层形成在侧壁对齐的间隔物上。 在第一反向材料层上形成并图案化第一光致抗蚀剂。 使用第一光致抗蚀剂作为掩模的第一反向材料层，其中侧壁对齐的间隔物不被蚀刻。 去除一个或多个虚拟线，并且使用侧壁对准的间隔件和第一反向材料层作为掩模来对硬掩模进行图案化。 用于形成侧壁对准间隔物的材料比用于形成第一反向材料层的材料具有更高的选择性。