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244 条记录 (耗时 0.036 秒)

    Semiconductor contact structure
    62.
    发明授权
    Semiconductor contact structure 有权
    半导体接触结构

    公开(公告)号：US07466028B1

    公开(公告)日：2008-12-16

    申请号：US11873037

    申请日：2007-10-16

    申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Hung-Jung Tu ,  Weng-Jin Wu

    发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Hung-Jung Tu ,  Weng-Jin Wu

    IPC分类号： H01L27/10 ,  H01L29/73 ,  H01L29/74 ,  H01L23/02 ,  H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L27/0688 ,  H01L23/481 ,  H01L25/0657 ,  H01L2223/6616 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device structure for a three-dimensional integrated circuit is provided. The semiconductor device structure includes: a substrate having a first surface and a second surface; a via defined in the substrate and extending from the first surface to the second surface; and a first plurality of contact structures on the first surface contacting the via. A cross section of each of the first plurality of contact structures parallel to the first surface has a first side and a second side, and a ratio of the longer side to the shorter side of the first side and the second side is more than about 2:1.

    摘要翻译： 提供了一种用于三维集成电路的半导体器件结构。 半导体器件结构包括：具有第一表面和第二表面的衬底; 通孔，其限定在所述基板中并且从所述第一表面延伸到所述第二表面; 以及在所述第一表面上接触所述通孔的第一多个接触结构。 平行于第一表面的第一多个接触结构中的每一个的横截面具有第一侧和第二侧，并且第一侧和第二侧的长边与短边的比例大于约2 ：1。

    Wafer Bonding
    63.
    发明申请
    Wafer Bonding 有权
    晶圆贴合

    公开(公告)号：US20080268614A1

    公开(公告)日：2008-10-30

    申请号：US11740178

    申请日：2007-04-25

    申请人： Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

    发明人： Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

    IPC分类号： H01L21/30

    CPC分类号： H01L21/2007

    摘要： A method for providing a stacked wafer configuration is provided. The method includes bonding a first wafer to a second wafer. A filler material is applied in a gap formed along edges of the first wafer and the second wafer. The filler material provides support along the edges during a thinning and transportation process to help reduce cracking or chipping. The filler material may be cured to reduce any bubbling that may have occurred while applying the filler material. Thereafter, the second wafer may be thinned by grinding, plasma etching, wet etching, or the like. In some embodiments of the present invention, this process may be repeated multiple times to create a stacked wafer configuration having three or more stacked wafers.

    摘要翻译： 提供一种用于提供堆叠晶片配置的方法。 该方法包括将第一晶片接合到第二晶片。 将填料施加在沿着第一晶片和第二晶片的边缘形成的间隙中。 填充材料在减薄和运输过程中沿着边缘提供支撑以帮助减少开裂或碎裂。 可以固化填充材料以减少在施加填充材料时可能发生的任何起泡。 此后，可以通过研磨，等离子体蚀刻，湿蚀刻等来减薄第二晶片。 在本发明的一些实施例中，该过程可以重复多次以产生具有三个或更多个堆叠晶片的堆叠晶片配置。

    Formation of through via before contact processing
    64.
    发明授权
    Formation of through via before contact processing 有权
    在联系处理之前形成通孔

    公开(公告)号：US09209157B2

    公开(公告)日：2015-12-08

    申请号：US13074883

    申请日：2011-03-29

    申请人： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu

    发明人： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu

    IPC分类号： H01L21/44 ,  H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L25/00

    CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

    摘要： The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.

    摘要翻译： 描述了在集成电路（IC）管芯或晶片中形成通孔硅通孔（TSV），其中在接触或金属化处理之前的集成工艺中形成TSV。 然后可以在TSV已经就位之后制造触点和接合焊盘，这允许TSV更致密并且允许TSV设计中的更多自由度。 通过在TSV和接合焊盘之间提供更密集的连接，单个晶片和管芯可以直接接合在接合焊盘处。 因此，导电接合材料通过接合焊盘保持与TSV和其它IC部件的电连接。

    Stacked structures and methods of forming stacked structures
    65.
    发明授权
    Stacked structures and methods of forming stacked structures 有权
    堆叠结构和形成堆叠结构的方法

    公开(公告)号：US08736039B2

    公开(公告)日：2014-05-27

    申请号：US11539481

    申请日：2006-10-06

    申请人： Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

    发明人： Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

    IPC分类号： H01L23/22

    CPC分类号： H01L21/78 ,  H01L23/585 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A stacked structure includes a first die bonded over a second die. The first die has a first die area defined over a first surface. At least one first protective structure is formed over the first surface, around the first die area. At least one side of the first protective structure has at least one first extrusion part extending across a first scribe line around the protective structure. The second die has a second die area defined over a second surface. At least one second protective structure is formed over the second surface, around the second die area. At least one side of the second protective structure has at least one second extrusion part extending across a second scribe line around the protective structure, wherein the first extrusion part is connected with the second extrusion part.

    摘要翻译： 层叠结构包括在第二管芯上结合的第一管芯。 第一管芯具有限定在第一表面上的第一管芯区域。 在第一表面，围绕第一模具区域形成至少一个第一保护结构。 第一保护结构的至少一侧具有至少一个在保护结构周围延伸穿过第一划线的第一挤压部分。 第二模具具有限定在第二表面上的第二模具区域。 在第二表面上围绕第二管芯区域形成至少一个第二保护结构。 第二保护结构的至少一侧具有至少一个在保护结构周围延伸穿过第二划线的第二挤压部分，其中第一挤压部分与第二挤压部分连接。

    Wafer bonding
    68.
    发明授权
    Wafer bonding 有权
    晶圆接合

    公开(公告)号：US08119500B2

    公开(公告)日：2012-02-21

    申请号：US11740178

    申请日：2007-04-25

    申请人： Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

    发明人： Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

    IPC分类号： H01L21/30

    CPC分类号： H01L21/2007

    摘要： A method for providing a stacked wafer configuration is provided. The method includes bonding a first wafer to a second wafer. A filler material is applied in a gap formed along edges of the first wafer and the second wafer. The filler material provides support along the edges during a thinning and transportation process to help reduce cracking or chipping. The filler material may be cured to reduce any bubbling that may have occurred while applying the filler material. Thereafter, the second wafer may be thinned by grinding, plasma etching, wet etching, or the like. In some embodiments of the present invention, this process may be repeated multiple times to create a stacked wafer configuration having three or more stacked wafers.

    摘要翻译： 提供了提供堆叠晶片配置的方法。 该方法包括将第一晶片接合到第二晶片。 将填料施加在沿着第一晶片和第二晶片的边缘形成的间隙中。 填充材料在减薄和运输过程中沿着边缘提供支撑以帮助减少开裂或碎裂。 可以固化填充材料以减少在施加填充材料时可能发生的任何起泡。 此后，可以通过研磨，等离子体蚀刻，湿蚀刻等来减薄第二晶片。 在本发明的一些实施例中，该过程可以重复多次以产生具有三个或更多个堆叠晶片的堆叠晶片配置。

    Particle free wafer separation
    70.
    发明授权
    Particle free wafer separation 有权
    无颗粒晶圆分离

    公开(公告)号：US08058150B2

    公开(公告)日：2011-11-15

    申请号：US12170494

    申请日：2008-07-10

    申请人： Weng-Jin Wu ,  Ku-Feng Yang ,  Jung-Chih Hu ,  Wen-Chih Chiou ,  Chen-Hua Yu

    发明人： Weng-Jin Wu ,  Ku-Feng Yang ,  Jung-Chih Hu ,  Wen-Chih Chiou ,  Chen-Hua Yu

    IPC分类号： H01L21/00

    CPC分类号： H01L21/78

    摘要： A method for singulating semiconductor wafers is disclosed. A preferred embodiment comprises forming scrub lines on one side of the wafer and filling the scrub lines with a temporary fill material. The wafer is then thinned by removing material from the opposite side of the wafer from the scrub lines, thereby exposing the temporary fill material on the opposite side. The temporary fill material is then removed, and the individual die are removed from the wafer.

    摘要翻译： 公开了一种用于分离半导体晶片的方法。 优选的实施方案包括在晶片的一侧上形成擦洗线，并用临时填充材料填充擦洗线。 然后通过从磨擦线从晶片的相对侧移除材料来使晶片变薄，从而在相对侧上暴露临时填充材料。 然后移除临时填充材料，并且将单个模具从晶片上移除。