公开(公告)号：US20240355805A1

公开(公告)日：2024-10-24

申请号：US18304350

申请日：2023-04-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Ting Yeh ,  Zheng-Yong Liang ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC分类号： H01L25/00 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L25/50 ,  H01L21/6835 ,  H01L24/08 ,  H01L24/83 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2224/08145 ,  H01L2224/80896 ,  H01L2224/83862

摘要： Provided is a method of forming a semiconductor structure including: bonding a device wafer onto a carrier wafer; forming a support structure between an edge of the device wafer and an edge of the carrier wafer, wherein the support structure surrounds a device layer of the device wafer along a closed path; removing a substrate and a portion of a bonding dielectric layer of the device wafer from a backside of the device wafer to expose the support structures while the support structure is in place; and removing the support structure through an acid etchant.

公开(公告)号：US20240355784A1

公开(公告)日：2024-10-24

申请号：US18758167

申请日：2024-06-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53209 ,  H01L24/33 ,  H01L24/83 ,  H01L25/50

摘要： A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via (TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.

公开(公告)号：US20240355771A1

公开(公告)日：2024-10-24

申请号：US18305569

申请日：2023-04-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Wei-Ting Chen ,  Chia-Chia Lin

IPC分类号： H01L23/00 ,  H01L23/522

CPC分类号： H01L24/32 ,  H01L23/5226 ,  H01L24/73 ,  H01L2224/32146 ,  H01L2224/73204

摘要： A method for forming a chip package structure is provided. The method includes providing a first substrate and a second substrate. The first substrate includes a first semiconductor base and a first bonding line over a front surface of the first semiconductor base, and the second substrate includes a second semiconductor base and a second bonding line over the second semiconductor base. The method includes bonding the second substrate to the first substrate. The first bonding line is in contact with the second bonding line. The method includes forming a conductive line over a back surface of the first semiconductor base. The conductive line is thicker than the first bonding line. The method includes forming a conductive bump over the back surface of the first semiconductor base. The conductive line is between the conductive bump and the first semiconductor base.

公开(公告)号：US20240355761A1

公开(公告)日：2024-10-24

申请号：US18760292

申请日：2024-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jiun-Yu Chen ,  Chun-Lin Tsai ,  Yun-Hsiang Wang ,  Chia-Hsun Wu ,  Jiun-Lei Yu ,  Po-Chih Chen

IPC分类号： H01L23/00 ,  H01L23/58 ,  H01L25/065 ,  H01L29/06

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2225/06541

摘要： In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor substrate includes a semiconductor material over a base substrate. The semiconductor substrate has one or more sidewalls forming a crack stop trench that is laterally between a central region of the semiconductor substrate and a peripheral region of the semiconductor substrate that surrounds the central region. The peripheral region of the semiconductor substrate includes a plurality of cracks.

公开(公告)号：US20240355756A1

公开(公告)日：2024-10-24

申请号：US18762685

申请日：2024-07-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chun-Hui Yu

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/365

摘要： Provided is a method of fabricating a package including: providing a die with a contact thereon; forming a redistribution layer (RDL) structure on the die, the forming the RDL structure on the die comprising: forming a first dielectric material on the die; forming a conductive feature in and partially on the first dielectric material; after the forming the conductive feature, forming a protective layer on the conductive feature, wherein the protective layer covers a top surface of the conductive feature and extends to cover a top surface of the first dielectric material; forming a second dielectric material on the protective layer; and performing a planarization process to expose the conductive feature; and forming a plurality of conductive connectors to electrically connect the die through the RDL structure.

公开(公告)号：US20240355741A1

公开(公告)日：2024-10-24

申请号：US18760444

申请日：2024-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shuen-Shin LIANG ,  Chun-I TSAI ,  Chih-Wei CHANG ,  Chun-Hsien HUANG ,  Hung-Yi HUANG ,  Keng-Chu LIN ,  Ken-Yu CHANG ,  Sung-Li WANG ,  Chia-Hung CHU ,  Hsu-Kai CHANG

IPC分类号： H01L23/532 ,  H01L21/285 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53266 ,  H01L21/76802 ,  H01L21/7685 ,  H01L21/28568 ,  H01L21/76843 ,  H01L23/5226

摘要： The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

公开(公告)号：US20240355721A1

公开(公告)日：2024-10-24

申请号：US18761200

申请日：2024-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Li-Hsien Huang ,  An-Jhih Su ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Chiang Lin ,  Ming-Shih Yeh

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10

CPC分类号： H01L23/49822 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/105 ,  H01L2225/1041 ,  H01L2225/1058

摘要： A semiconductor package includes a semiconductor die including an active surface and an electrical terminal on the active surface, and a redistribution circuitry disposed on the active surface of the semiconductor die and connected to the electrical terminal. A top surface of the redistribution circuitry includes a planar portion and a concave portion connected to the planar portion, the concave portion is directly over the electrical terminal, and a minimum distance measured from a lowest point of the concave portion to a virtual plane where the planar portion is located is equal to or smaller than 0.5 μm.

公开(公告)号：US20240355708A1

公开(公告)日：2024-10-24

申请号：US18304913

申请日：2023-04-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Yu HUANG ,  Shih-Chieh WU ,  Chen-Ming LEE ,  I-Wen WU ,  Fu-Kai YANG ,  Mei-Yun WANG

IPC分类号： H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

摘要： One aspect of the present disclosure pertains to a method of forming a semiconductor device. The method includes forming a gate stack over a channel region and forming a first source/drain (S/D) trench adjacent the channel region and extending into the substrate below a top surface of an isolation structure. The method includes forming a first epitaxial S/D feature in the first S/D trench and forming a first frontside metal contact over the first epitaxial S/D feature. The method further includes forming a first backside trench that exposes a bottom surface of the first epitaxial S/D feature and forming a first backside conductive feature in the first backside trench and on the exposed bottom surface of the first epitaxial S/D feature. A top surface of the first backside conductive feature is under a bottommost surface of the gate stack.

公开(公告)号：US20240355680A1

公开(公告)日：2024-10-24

申请号：US18758926

申请日：2024-06-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Cheng Chou ,  Ying-Liang Chuang ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC分类号： H01L21/8234 ,  H01L21/033 ,  H01L21/311

CPC分类号： H01L21/823431 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31133

摘要： A method for manufacturing a semiconductor device includes forming one or more work function layers over a semiconductor structure. The method includes forming a hardmask layer over the one or more work function layers. The method includes forming an adhesion layer over the hardmask layer. The method includes removing a first portion of a patternable layer that is disposed over the hardmask layer. The adhesion layer comprises an organic acid that concurrently bonds metal atoms of the hardmask layer and phenol groups of the patternable layer, thereby preventing an etchant from penetrating into a second portion of the patternable layer that still remains over the hardmask layer.

公开(公告)号：US20240355625A1

公开(公告)日：2024-10-24

申请号：US18758948

申请日：2024-06-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/033 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/28185 ,  H01L21/02603 ,  H01L21/0332 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78696

摘要： A structure includes first nanostructures vertically spaced one from another over a substrate in a core region of the semiconductor structure, a first interfacial layer wrapping around each of the first nanostructures, a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures, second nanostructures vertically spaced one from another over the substrate in an I/O region of the semiconductor structure, a second interfacial layer wrapping around each of the second nanostructures, a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures. The first nanostructures have a first vertical pitch, the second nanostructures have a second vertical pitch substantially equal to the first vertical pitch, the first nanostructures have a first vertical spacing, the second nanostructures have a second vertical spacing greater than the first vertical spacing by about 4 Å to about 20 Å.