公开(公告)号：US07883996B2

公开(公告)日：2011-02-08

申请号：US12817817

申请日：2010-06-17

申请人： Masaki Ueno

发明人： Masaki Ueno

IPC分类号： H01L33/00

CPC分类号： H01L29/34 ,  C30B25/18 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/2003 ,  H01L33/16 ,  Y10T83/04

摘要： A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more single crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a mirror polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An axis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface.

摘要翻译： 制造单晶氮化镓衬底的方法是将单晶氮化镓锭沿着预定平面切割以制造一个或多个单晶氮化镓衬底的步骤。 单晶氮化镓锭通过气相外延沿预定轴线的方向生长。 每个预定平面相对于预定轴线倾斜。 每个基板具有镜面抛光的主表面。 主表面具有第一区域和第二区域。 第一区域位于衬底的边缘和距离边缘3毫米的线之间。 第一个区域围绕第二个区域。 垂直于主表面的轴与衬底的c轴形成偏角。 偏角在主表面的第一区域中的第一位置处具有最小值。

公开(公告)号：US20100092888A1

公开(公告)日：2010-04-15

申请号：US12576490

申请日：2009-10-09

申请人： Brent A. Buchine ,  Faris Modawar ,  Marcie R. Black

发明人： Brent A. Buchine ,  Faris Modawar ,  Marcie R. Black

IPC分类号： G03F7/20 ,  B32B3/10 ,  B32B15/00 ,  C23F1/00 ,  H01L33/00 ,  H01L31/0216

CPC分类号： H01L29/34 ,  B81C1/00619 ,  H01L21/30604

摘要： A process for etching a silicon-containing substrate to form structures is provided. In the process, a metal is deposited and patterned onto a silicon-containing substrate (commonly one with a resistivity above 1-10 ohm-cm) in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is submerged into an etchant aqueous solution comprising about 4 to about 49 weight percent HF and an oxidizing agent such as about 0.5 to about 30 weight percent H2O2, thus producing a metallized substrate with one or more trenches. A second silicon etch is optionally employed to remove nanowires inside the one or more trenches.

摘要翻译： 提供了一种用于蚀刻含硅衬底以形成结构的工艺。 在该过程中，将金属沉积并图案化到含硅衬底（通常具有高于1-10欧姆 - 厘米电阻率的衬底），使得金属存在并接触需要蚀刻并被阻挡的硅 触摸硅或其他地方不存在。 将金属化衬底浸入包含约4至约49重量％的HF和氧化剂如约0.5至约30重量％的H 2 O 2的蚀刻剂水溶液中，从而产生具有一个或多个沟槽的金属化衬底。 任选地使用第二硅蚀刻来去除一个或多个沟槽内的纳米线。

公开(公告)号：US20080003782A1

公开(公告)日：2008-01-03

申请号：US11482237

申请日：2006-07-03

申请人： David Lysacek ,  Michal Lorenc ,  Lukas Valek

发明人： David Lysacek ,  Michal Lorenc ,  Lukas Valek

IPC分类号： H01L21/322 ,  H01L21/8222

CPC分类号： H01L29/7322 ,  H01L21/3221 ,  H01L29/34

摘要： In one embodiment, a multi-layer extrinsic gettering structure includes plurality of polycrystalline semiconductor layers each separated by a dielectric layer.

摘要翻译： 在一个实施例中，多层外部吸气结构包括多个多层半导体层，每个多晶半导体层由电介质层分隔开。

公开(公告)号：US20050227438A1

公开(公告)日：2005-10-13

申请号：US11140756

申请日：2005-05-31

申请人： Yoshifumi Okabe ,  Masami Yamaoka ,  Akira Kuroyanagi

发明人： Yoshifumi Okabe ,  Masami Yamaoka ,  Akira Kuroyanagi

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/304 ,  H01L21/336 ,  H01L29/06 ,  H01L29/167 ,  H01L29/34 ,  H01L29/417 ,  H01L29/45 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7802 ,  H01L21/28 ,  H01L21/28512 ,  H01L21/304 ,  H01L29/0657 ,  H01L29/167 ,  H01L29/34 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/10158 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/938 ,  Y10S438/964 ,  Y10S438/977 ,  H01L2924/00

摘要： A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

摘要翻译： 一种半导体器件，包括包含砷作为杂质的N型半导体衬底，形成在N型半导体衬底的主表面上的第一电极，形成在N型半导体衬底的另一表面上的接地表面，第二 电极，其形成在地表面上并与N型半导体衬底欧姆接触，形成在N型半导体衬底中的半导体元件和在其第一电极和第二电极之间的流动电流。 该器件具有降低的导通电阻。

公开(公告)号：US06927167B2

公开(公告)日：2005-08-09

申请号：US10732376

申请日：2003-12-11

申请人： Yutaka Fukuda ,  Naohiko Hirano ,  Chikage Noritake ,  Shoji Miura

发明人： Yutaka Fukuda ,  Naohiko Hirano ,  Chikage Noritake ,  Shoji Miura

IPC分类号： H01L21/28 ,  H01L21/304 ,  H01L21/306 ,  H01L21/331 ,  H01L21/336 ,  H01L23/433 ,  H01L23/495 ,  H01L29/34 ,  H01L29/41 ,  H01L29/78 ,  H01L21/302

CPC分类号： H01L24/33 ,  H01L21/304 ,  H01L21/30604 ,  H01L23/4334 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/48 ,  H01L29/34 ,  H01L29/66333 ,  H01L2224/05599 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing a semiconductor device with a substrate having a device layer and a backside electrode is disclosed. Here, a surface roughness of the substrate is defined as a ratio between a substantial area and a projected area. The method includes polishing and wet-etching a backside surface of the substrate mechanically with using predetermined abrasive grains so that a surface roughness of the backside surface of the substrate becomes to be equal to or larger than 1.04, and forming the backside electrode on the backside surface of the substrate after polishing and wet-etching the backside surface of the substrate.

摘要翻译： 公开了一种具有具有器件层和背面电极的衬底的半导体器件的制造方法。 这里，基板的表面粗糙度被定义为实质面积和投影面积之间的比率。 该方法包括使用预定的磨粒机械地抛光和湿法蚀刻衬底的背面，使得衬底的背面的表面粗糙度等于或大于1.04，并且在背面形成背面电极 抛光后的基板的表面和湿法蚀刻基板的背面。

公开(公告)号：US06707130B2

公开(公告)日：2004-03-16

申请号：US10279055

申请日：2002-10-24

申请人： Hidenori Fujii

发明人： Hidenori Fujii

IPC分类号： H01L29732

CPC分类号： H01L29/66272 ,  H01L29/1004 ,  H01L29/34

摘要： A first dopant impurity producing a conductivity type for formation of an intrinsic base diffusion layer and a dopant impurity producing the opposite conductivity type are implanted into a semiconductor substrate. An exposed surface of the semiconductor substrate is irradiated with a plasma, so that many crystalline defects are produced. Next, a polysilicon film is formed under conditions that cause the grain size to increase. In a portion of the polysilicon film located near the exposed surface of the semiconductor substrate, the grain size becomes relatively small, influenced by the crystalline defects in the substrate surface. In a portion of the polysilicon film located on the silicon oxide film, the grain size becomes relatively large, uninfluenced by the crystalline defects. Thus, degradation of electrical characteristics is suppressed, and variation in resistance of the resistance element is alleviated.

摘要翻译： 产生用于形成本征基极扩散层的导电类型和产生相反导电类型的掺杂剂杂质的第一掺杂剂杂质被注入到半导体衬底中。 用等离子体照射半导体衬底的暴露表面，从而产生许多晶体缺陷。 接下来，在导致晶粒尺寸增加的条件下形成多晶硅膜。 在位于半导体衬底的暴露表面附近的多晶硅膜的一部分中，晶粒尺寸变得相对较小，受到衬底表面中的晶体缺陷的影响。 在位于氧化硅膜上的多晶硅膜的一部分中，晶粒尺寸变得相对较大，不受结晶缺陷的影响。 因此，电特性的劣化被抑制，并且电阻元件的电阻的变化得到缓解。

公开(公告)号：US5939770A

公开(公告)日：1999-08-17

申请号：US143251

申请日：1998-08-28

申请人： Mokuji Kageyama

发明人： Mokuji Kageyama

IPC分类号： H01L21/322 ,  H01L29/32 ,  H01L29/34 ,  H01L29/24 ,  H01L29/36

CPC分类号： H01L29/32 ,  H01L21/3225 ,  H01L29/34 ,  Y10S257/913

摘要： A denuded zone DZ least liable to generate defects is formed in a surface layer zone 12 of a semiconductor wafer 10. In an inner layer zone 18 of the semiconductor wafer 10, micro defects BMD for gettering of impurity metal are made. In the inner layer zone 18, the precipitation of oxygen decreases with the depth. As a result, mechanical strength can be maintained while improving the gettering performance of impurity metal.

公开(公告)号：US5689130A

公开(公告)日：1997-11-18

申请号：US409900

申请日：1995-03-22

申请人： Yoshifumi Okabe ,  Masami Yamaoka ,  Akira Kuroyanagi

发明人： Yoshifumi Okabe ,  Masami Yamaoka ,  Akira Kuroyanagi

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/304 ,  H01L21/336 ,  H01L29/06 ,  H01L29/167 ,  H01L29/34 ,  H01L29/417 ,  H01L29/45 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L29/66712 ,  H01L21/28 ,  H01L21/28512 ,  H01L21/304 ,  H01L29/0657 ,  H01L29/34 ,  H01L29/41741 ,  H01L29/7802 ,  H01L29/167 ,  H01L29/456 ,  H01L2924/0002 ,  H01L2924/10158 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/938 ,  Y10S438/964 ,  Y10S438/977

摘要： A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

摘要翻译： 一种半导体器件，包括包含砷作为杂质的N型半导体衬底，形成在N型半导体衬底的主表面上的第一电极，形成在N型半导体衬底的另一表面上的接地表面，第二 电极，其形成在地表面上并与N型半导体衬底欧姆接触，形成在N型半导体衬底中的半导体元件和在其第一电极和第二电极之间的流动电流。 该器件具有降低的导通电阻。

公开(公告)号：US20240312779A1

公开(公告)日：2024-09-19

申请号：US18677887

申请日：2024-05-30

申请人： FILNEX INC.

发明人： Mitsuhiko OGIHARA ,  Akihiro HASHIMOTO

IPC分类号： H01L21/02 ,  H01L21/67 ,  H01L29/34

CPC分类号： H01L21/02444 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/67098 ,  H01L29/34

摘要： A semiconductor substrate manufacturing method includes the steps of: forming, on a first surface of a first substrate, a plurality of terrace portions arranged in a first direction parallel to a horizontal plane of the first substrate, and a step portion having a predetermined height between two adjacent terrace portions in the first direction; forming a first semiconductor layer such that a part of the step portion is exposed; and vaporizing a portion of Si of the first substrate from a part of the step portion exposed from the first semiconductor layer by performing heat treatment on the first substrate on which the first semiconductor layer is formed, thereby forming a buffer layer having at least one graphene layer in at least a part between the first semiconductor layer and the first substrate.

公开(公告)号：US20240290616A1

公开(公告)日：2024-08-29

申请号：US18435035

申请日：2024-02-07

申请人： DENSO CORPORATION ,  FUJI ELECTRIC CO., LTD.

发明人： Tomohiro MIMURA ,  Kensuke HATA ,  Masanobu IWAYA

IPC分类号： H01L21/04 ,  H01L23/34 ,  H01L29/06 ,  H01L29/16 ,  H01L29/34 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/045 ,  H01L21/046 ,  H01L23/34 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/34 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/7813

摘要： A silicon carbide semiconductor device has a semiconductor substrate, a trench gate structure disposed in the semiconductor substrate, a first electrode electrically connected to an impurity region and a bae layer of the semiconductor substrate, a second electrode connected to a substrate, and an interlayer insulating film disposed between a gate electrode and the first electrode. The trench gate structure includes a gate insulating film disposed in a trench of the semiconductor substrate and the gate electrode disposed on the gate insulating film. A portion of the semiconductor substrate adjoining the trench has a termination structure in which dangling bonds are terminated with at least one of nitrogen, hydrogen or phosphorous. The interlayer insulating film has a contact insulating film that is in contact with the gate electrode. The contact insulating film is provided by a deposited film.