公开(公告)号：US09704875B2

公开(公告)日：2017-07-11

申请号：US15259502

申请日：2016-09-08

Applicant: Renesas Electronics Corporation

Inventor： Tadashi Yamaguchi

IPC: H01L27/115 ,  H01L27/11568 ,  H01L29/45 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/285 ,  H01L21/321 ,  H01L21/28 ,  H01L27/11521 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/3212 ,  H01L27/11521 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: When upper surfaces of a control gate electrode and a memory gate electrode are exposed from an interlayer insulating film by polishing the interlayer insulating film in a gate last process, a silicide layer covering the upper surfaces of the gate electrodes is formed. Thereafter, by reacting a metal film deposited on the silicide layer with the control gate electrode and the memory gate electrode, a silicide layer thicker than the former silicide layer is formed on each of the gate electrodes.

公开(公告)号：US20170170189A1

公开(公告)日：2017-06-15

申请号：US14967813

申请日：2015-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H01L27/115 ,  H01L29/49 ,  H01L21/321 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/32115 ,  H01L21/32139 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a logic region having a logic device disposed over a substrate and including a first metal gate disposed over a first high-k gate dielectric layer and an embedded memory region disposed adjacent to the logic region. The embedded memory region has a split gate flash memory cell including a select gate and a control gate. The control gate or the select gate is a metal gate separated from the substrate by a second high-k gate dielectric layer. By having HKMG structures in both the logic region and the memory region, IC performance is improved and further scaling becomes possible in emerging technology nodes.

公开(公告)号：US20170170188A1

公开(公告)日：2017-06-15

申请号：US14967767

申请日：2015-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H01L27/115 ,  H01L29/51 ,  H01L21/28 ,  H01L29/45 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66833

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a logic region and an embedded memory region disposed adjacent to the logic region. The logic region has a logic device disposed over a substrate and including a first metal gate disposed over a first high-k gate dielectric layer. The memory region has a non-volatile memory (NVM) device including a second metal gate disposed over a second high-k gate dielectric layer. By having HKMG structures in both the logic region and the memory region, IC performance is improved and further scaling becomes possible in emerging technology nodes.

公开(公告)号：US09659943B1

公开(公告)日：2017-05-23

申请号：US15063963

申请日：2016-03-08

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Xuan Anh Tran ,  Eng Huat Toh

IPC: H01L27/11 ,  H01L21/82 ,  H01L29/423 ,  H01L27/112 ,  H01L29/06 ,  H01L29/08 ,  H01L23/528 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/1157 ,  H01L29/78 ,  H01L27/11524 ,  H01L27/11517 ,  H01L27/115

CPC classification number: H01L27/11206 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/5252 ,  H01L23/528 ,  H01L27/0886 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/7841

Abstract: Integrated circuits and methods of forming the same are provided. An exemplary integrated circuit includes a semiconductor substrate having a central shallow trench isolation (STI) region. A pair of select transistors have drain regions in contact with opposite portions of the central STI region. A central gate structure overlies the central STI region and includes a central gate dielectric layer. The central gate dielectric layer has a medial dielectric region overlying the central STI region, a first lateral dielectric region overlying the first drain region, and a second lateral dielectric region overlying the second drain region. The first lateral dielectric region defines a first programmable element and the second lateral dielectric region defines a second programmable element.

公开(公告)号：US20170141201A1

公开(公告)日：2017-05-18

申请号：US15281010

申请日：2016-09-29

Applicant: Cypress Semiconductor Corporation

Inventor： Shenqing Fang ,  Chun Chen ,  Unsoon Kim ,  Mark Ramsbey ,  Kuo Tung Chang ,  Sameer Haddad ,  James Pak

IPC: H01L29/423 ,  H01L29/792 ,  H01L21/02 ,  H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/42344 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573 ,  H01L28/00 ,  H01L29/42328 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.

公开(公告)号：US20170141120A1

公开(公告)日：2017-05-18

申请号：US14941835

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Chiang Min ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Yuan-Tai Tseng

IPC: H01L27/115 ,  H01L29/792 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/11568 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/792

Abstract: Provided is a method of forming a decoupling capacitor device and the device thereof. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.

公开(公告)号：US20170133388A1

公开(公告)日：2017-05-11

申请号：US14933046

申请日：2015-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

公开(公告)号：US09640259B2

公开(公告)日：2017-05-02

申请号：US14946796

申请日：2015-11-20

Applicant: eMemory Technology Inc.

Inventor： Yi-Hung Li ,  Yen-Hsin Lai ,  Ming-Shan Lo ,  Shih-Chan Huang

IPC: H01L27/108 ,  G11C16/10 ,  H01L29/788 ,  G11C16/14 ,  H01L27/02 ,  H01L27/115 ,  G11C16/04 ,  H01L27/11558 ,  H01L29/51 ,  H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L29/06 ,  H01L29/423 ,  G11C16/24 ,  H01L27/11524 ,  G11C16/34 ,  G11C16/26 ,  H01L29/45

CPC classification number: G11C16/0433 ,  G11C16/0416 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2216/10 ,  H01L27/11524 ,  H01L27/11558 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/45 ,  H01L29/512 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7882 ,  H01L29/792

Abstract: A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.

公开(公告)号：US20170110202A1

公开(公告)日：2017-04-20

申请号：US14883791

申请日：2015-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien ,  Fang-Lan Chu ,  Hong-Da Lin ,  Ku-Ning Chang ,  Yu-Chen Wang

IPC: G11C29/02 ,  H01L23/528 ,  H01L29/51 ,  G01R31/26 ,  H01L27/115 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/544 ,  H01L29/49

CPC classification number: G01R31/2644 ,  H01L21/32133 ,  H01L21/76877 ,  H01L22/34 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11568 ,  H01L27/11573 ,  H01L28/00 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L2223/54406 ,  H01L2223/54453 ,  H01L2223/5446

Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.

公开(公告)号：US09620604B2

公开(公告)日：2017-04-11

申请号：US15014267

申请日：2016-02-03

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Anirban Roy ,  Ko-Min Chang

IPC: H01L29/788 ,  H01L29/792 ,  H01L27/11521 ,  H01L29/423 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11568

CPC classification number: H01L29/42348 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.