公开(公告)号：US09910605B2

公开(公告)日：2018-03-06

申请号：US15353431

申请日：2016-11-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan S. Jayasena ,  Gabriel H. Loh ,  James M. O'Connor ,  Niladrish Chatterjee

IPC: G06F3/06 ,  G06F12/06 ,  G06F12/0811

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/205 ,  G11C11/005 ,  Y02D10/13

Abstract: A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more memory dies, the set of one or more logic dies comprising a memory interface and a page migration manager, the memory interface coupleable to a device external to the die-stacked hybrid memory device, and the page migration manager to transfer memory pages between the first set of one or more memory dies and the second set of one or more memory dies.

公开(公告)号：US09898568B2

公开(公告)日：2018-02-20

申请号：US14748075

申请日：2015-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Naveen Chandra Srivastava ,  Janardhan Achanta ,  Pankaj Kumar ,  Shreekanth Karandoor Sampigethaya

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  G06F2217/78

Abstract: Systems, apparatuses, and methods for reducing the load on the bitlines of a ROM bitcell array are described. The connections between nets of a ROM bitcell array may be assigned based on their programmed values using a traditional approach. Then, a plurality of optimizations may be performed on the assignment of nets to reduce the load on the bitlines of the array. A first optimization may swap the connections between ground and bitline for the nets of a given column responsive to detecting that the number of connections to the corresponding bitline is greater than the number of connections to ground for the given column. A second optimization may remove the connection of a net to a bitline if three consecutive nets of a given column are connected to the bitline.

公开(公告)号：US09898287B2

公开(公告)日：2018-02-20

申请号：US14682971

申请日：2015-04-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Sooraj Puthoor ,  Bradford M. Beckmann ,  Dmitri Yudanov

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/46

CPC classification number: G06F9/30058 ,  G06F9/3804 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/46

Abstract: A method, a non-transitory computer readable medium, and a processor for repacking dynamic wavefronts during program code execution on a processing unit, each dynamic wavefront including multiple threads are presented. If a branch instruction is detected, a determination is made whether all wavefronts following a same control path in the program code have reached a compaction point, which is the branch instruction. If no branch instruction is detected in executing the program code, a determination is made whether all wavefronts following the same control path have reached a reconvergence point, which is a beginning of a program code segment to be executed by both a taken branch and a not taken branch from a previous branch instruction. The dynamic wavefronts are repacked with all threads that follow the same control path, if all wavefronts following the same control path have reached the branch instruction or the reconvergence point.

公开(公告)号：US20180039531A1

公开(公告)日：2018-02-08

申请号：US15231251

申请日：2016-08-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel I. Lowell ,  Manish Gupta

IPC: G06F11/07 ,  G06F9/30

CPC classification number: G06F11/0763 ,  G06F9/30021 ,  G06F9/30101 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3887 ,  G06F11/0721 ,  G06F11/0784

Abstract: Techniques for performing redundant multi-threading (“RMT”) include the use of an RMT compare instruction by two program instances (“work-items”). The RMT compare instruction specifies a value from each work-item to be compared. Upon executing the RMT compare instructions, the work-items transmit the values to a hardware comparator unit. The hardware comparator unit compares the received values and performs an error action if the values do not match. The error action may include sending an error code in a return value back to the work-items that requested the comparison or emitting a trap signal. Optionally, the work-items also send addresses for comparison to the comparator unit. If the addresses and values match, then the comparator stores the value at the specified address. If either or both of the values or the addresses do not match, then the comparator performs an error action.

公开(公告)号：US20180018291A1

公开(公告)日：2018-01-18

申请号：US15211815

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Jackson Peng ,  Hideki Kanayama

IPC: G06F13/16 ,  G06F13/40

Abstract: In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.

公开(公告)号：US09870473B2

公开(公告)日：2018-01-16

申请号：US14529278

申请日：2014-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Denis Rystsov ,  Sebastien Nussbaum

IPC: H04L29/06 ,  G06F21/57 ,  G06F21/50 ,  G06F1/26 ,  G06F21/81 ,  G06F1/32

CPC classification number: G06F21/57 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3287 ,  G06F21/50 ,  G06F21/81 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/128 ,  Y02D10/171

Abstract: The present disclosure presents methods and apparatuses for controlling a power state, which may include a C-state, of one or more processing cores of a processor. In an aspect, an example method of securing a power state change of a processor is presented, the method including the steps of receiving a power state change request from the processor, the processor having a plurality of potential power states each including an operating power profile; determining a power state change request mode associated with the processor; forwarding the power state change request to a security processor where the power state change request mode is a one-time request mode; receiving a power state change request response from the security processor in response to the request; and adjusting the current power state of the processor to the target power state where the power state change request response comprises a power state change approval.

公开(公告)号：US20180011798A1

公开(公告)日：2018-01-11

申请号：US15695683

申请日：2017-09-05

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony ASARO ,  Kevin NORMOYLE ,  Mark HUMMEL

IPC: G06F12/06 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/0284 ,  G06F12/0646 ,  G06F12/08 ,  G06F12/10 ,  G06F12/109 ,  G06F2212/1012 ,  G06F2212/152 ,  G06F2212/656 ,  G06F2212/657

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

公开(公告)号：US09851777B2

公开(公告)日：2017-12-26

申请号：US14146591

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan S. Jayasena ,  Srilatha Manne ,  Madhu Saravana Sibi Govindan ,  William L. Bircher

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3225 ,  Y02D10/171 ,  Y02D50/20

Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.

公开(公告)号：US09837398B1

公开(公告)日：2017-12-05

申请号：US15360168

申请日：2016-11-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Omid Rowhani ,  Jason P. Cain ,  Ioan Cordos ,  Michael Davinson Sherriff ,  Hoang Q. Dao

IPC: H01L27/118 ,  H01L27/02 ,  H01L29/06 ,  H01L23/528 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  G06F17/5077 ,  H01L27/11807 ,  H01L2027/11875

Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

公开(公告)号：US20170345512A1

公开(公告)日：2017-11-30

申请号：US15267092

申请日：2016-09-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Amro Awad ,  Sergey Blagodurov

IPC: G11C16/34 ,  G11C16/10 ,  G06F3/06 ,  G11C16/26

CPC classification number: G11C16/3495 ,  G11C16/10 ,  G11C16/26

Abstract: A non-volatile memory device having at least one non-volatile flash memory formatted with physical addresses to read and write data that is organized into blocks of data, wherein the blocks of data are organized into pages of data, and wherein the pages of data are organized into cells of data. The non-volatile memory device includes a non-volatile memory controller to direct read and write requests to the non-volatile flash memory for the storage and retrieval of data. The non-volatile memory controller includes a flash translation layer to correlate read and write requests for data having a logical address between the reading and writing the data to physical address location of the non-volatile flash memory. The flash translation layer, when writing to a physical address location, chooses between a wear-leveling circuit and a wear-limiting circuit to select the physical address location.