公开(公告)号：US20240321339A1

公开(公告)日：2024-09-26

申请号：US18634799

申请日：2024-04-12

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G06F11/10 ,  G11C7/02 ,  G11C11/4096 ,  G11C29/04 ,  G11C29/52

CPC classification number: G11C11/4093 ,  G06F11/1048 ,  G11C7/02 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single-and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US20240282354A1

公开(公告)日：2024-08-22

申请号：US18590221

申请日：2024-02-28

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/406 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/02

CPC classification number: G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US20240276639A1

公开(公告)日：2024-08-15

申请号：US18604133

申请日：2024-03-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan

IPC: H05K1/11 ,  G06F1/18 ,  G06F13/16 ,  G06F13/40 ,  G06F15/78 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4093 ,  H05K1/18

CPC classification number: H05K1/11 ,  G06F1/184 ,  G06F13/1694 ,  G06F13/4068 ,  G06F15/7803 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4082 ,  G11C11/4093 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

公开(公告)号：US20240242751A1

公开(公告)日：2024-07-18

申请号：US18399096

申请日：2023-12-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G11C11/406 ,  G06F13/16

CPC classification number: G11C11/40611 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4067 ,  Y02D10/00

Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

公开(公告)号：US20240241824A1

公开(公告)日：2024-07-18

申请号：US18422073

申请日：2024-01-25

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1009

CPC classification number: G06F12/0253 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1009 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/60 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

公开(公告)号：US12002532B2

公开(公告)日：2024-06-04

申请号：US18121220

申请日：2023-03-14

Applicant: Rambus Inc.

Inventor： John Eric Linstadt ,  Frederick A. Ware

IPC: G11C29/42 ,  G11C8/18 ,  G11C29/18 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C8/18 ,  G11C29/18 ,  G11C29/44

Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.

公开(公告)号：US11996160B2

公开(公告)日：2024-05-28

申请号：US17892291

申请日：2022-08-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Carl W. Werner

IPC: G11C7/04 ,  G06F1/12 ,  G11C7/22 ,  G11C29/02 ,  G11C29/50 ,  H03K5/15 ,  H10N60/12

CPC classification number: G11C7/04 ,  G06F1/12 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/15 ,  H10N60/12

Abstract: In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal. The second IC has an interface coupled to the signaling link and timed by a second interface timing signal that is mesochronous with respect to the first interface timing signal. The second IC further has phase adjustment circuitry that adjusts a phase of the second interface timing signal using a digital counter implemented with Josephson-junction circuit elements.

公开(公告)号：US11994930B2

公开(公告)日：2024-05-28

申请号：US17748704

申请日：2022-05-19

Applicant: Rambus Inc.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G06F1/324 ,  G06F1/3234 ,  G06F1/3287 ,  G06F5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C7/04 ,  H03L7/081

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G06F2205/067 ,  G11C7/04 ,  G11C2207/2272 ,  H03L7/0816

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

公开(公告)号：US20240160587A1

公开(公告)日：2024-05-16

申请号：US18513246

申请日：2023-11-17

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright ,  John Eric Linstadt ,  Craig Hampel

IPC: G06F13/16 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/0895 ,  G06F13/28 ,  G11C7/10 ,  G11C29/52

CPC classification number: G06F13/1678 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1068 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/0895 ,  G06F13/28 ,  G11C7/10 ,  G11C29/52 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/403

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

公开(公告)号：US20240153548A1

公开(公告)日：2024-05-09

申请号：US18503022

申请日：2023-11-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Thomas Vogelsang ,  Michael Raymond Miller ,  Collins Williams

IPC: G11C11/4093 ,  G06F12/0895 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/4093 ,  G06F12/0895 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087 ,  G11C2207/2245

Abstract: Disclosed is a memory system including a memory component having at least one tag row and at least one data row and multiple ways to hold a data group as a cache-line or cache-block. The memory system includes a memory controller that is connectable to the memory component to implement a cache and operable with the memory controller and the memory component in each of a plurality of operating modes including a first and second operating mode having differing addressing and timing requirements for accessing the data group. The first operating mode having placement of each of at least two ways of a data group in differing rows in the memory component, with tag access and data access not overlapped. The second operating mode having placement of all ways of a data group in a same row in the memory component, with tag access and data access overlapped.