公开(公告)号：US20240213235A1

公开(公告)日：2024-06-27

申请号：US18089459

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/1427 ,  H01L2924/1431

Abstract: An apparatus is provided which comprises: an integrated circuit logic device, an integrated circuit power device conductively coupled with a first surface of the integrated circuit logic device, wherein the integrated circuit power device extends laterally beyond a side of the integrated circuit logic device, one or more vias adjacent the side of the integrated circuit logic device extending from contact with the integrated circuit power device to level with a second surface of the integrated circuit logic device opposite the first surface of the integrated circuit logic device, and conductive contacts on the second surface of the integrated circuit logic device. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240213216A1

公开(公告)日：2024-06-27

申请号：US18597684

申请日：2024-03-06

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Amr Elshazly ,  Arun CHANDRASEKHAR ,  Shawna M. LIFF ,  Johanna M. SWAN

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L23/49822 ,  H01L25/50

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

公开(公告)号：US20240213163A1

公开(公告)日：2024-06-27

申请号：US18089417

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Jung Kyu Han

IPC: H01L23/535 ,  H01L23/00 ,  H01L23/538 ,  H01L23/544 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/535 ,  H01L23/5381 ,  H01L23/5386 ,  H01L23/544 ,  H01L23/66 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L2224/165 ,  H01L2224/32225

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes vertical connections with a layer including tin between the vertical connections and conductive traces. In selected examples, a layer including tin is used in conjunction with other interface layers. In selected examples, a layer including tin is used in all vertical connections.

公开(公告)号：US20240213156A1

公开(公告)日：2024-06-27

申请号：US18089491

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Tarek A. IBRAHIM ,  Aaron GARELICK ,  Srikant NEKKANTY ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/532 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/522 ,  H01L23/535 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/53209 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/535 ,  H01L23/642 ,  H01L24/05 ,  H01L24/29 ,  H01L25/0655 ,  H01L2224/04026 ,  H01L2224/05567 ,  H01L2224/29007 ,  H01L2224/29021 ,  H01L2224/29101 ,  H01L2924/1436 ,  H01L2924/15321

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core and buildup layers over the core. In an embodiment, a pad is provided on the buildup layers. In an embodiment, a liquid metal well is over the pad.

公开(公告)号：US20240213132A1

公开(公告)日：2024-06-27

申请号：US18089476

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Benjamin DUONG ,  Darko GRUJICIC ,  Shayan KAVIANI ,  Mahdi MOHAMMADIGHALENI ,  Suddhasattwa NAD ,  Thomas L. SOUNART ,  Marcel WALL ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/498 ,  H01L27/01

CPC classification number: H01L23/49838 ,  H01L27/016 ,  H01L28/86 ,  H01L28/90 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of stacked dielectric layers. In an embodiment, the electronic package further comprises an opening into the package substrate, where the opening passes through at least two of the plurality of dielectric layers. In an embodiment, a first pad is at the bottom of the opening, a capacitor is disposed in the opening, and a second pad is over the capacitor.

公开(公告)号：US20240213118A1

公开(公告)日：2024-06-27

申请号：US18088545

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Heli Chetanbhai VORA ,  Samuel James BADER ,  Ahmad ZUBAIR ,  Thomas HOFF ,  Pratik KOIRALA ,  Michael S. BEUMER ,  Paul NORDEEN ,  Nityan NAIR

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778 ,  H01P3/00

CPC classification number: H01L23/481 ,  H01L23/5286 ,  H01L23/53228 ,  H01L23/66 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H01P3/003 ,  H01L2223/6627

Abstract: Gallium nitride (GaN) devices with through-silicon vias for integrated circuit technology are described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, the layer including gallium and nitrogen above a silicon substrate. A backside structure is below the silicon substrate and opposite the layer including gallium and nitrogen, the backside structure including conductive features and dielectric structures. The integrated circuit structure also includes a plurality of through-silicon via power bars having a staggered arrangement, individual ones of the through-silicon via power bars extending through the layer including gallium and nitrogen and through the silicon substrate to a corresponding one of the conductive features of the backside structure, and individual ones of the through-silicon via power bars having a tapered portion coupled to an essentially vertical portion.

公开(公告)号：US20240213116A1

公开(公告)日：2024-06-27

申请号：US18069507

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Kyle Arrington ,  Bohan Shan ,  Haobo Chen ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Dingying Xu ,  Xiaoying Guo ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L23/473 ,  H01L23/15 ,  H01L23/467 ,  H01L23/538

CPC classification number: H01L23/473 ,  H01L23/15 ,  H01L23/467 ,  H01L23/5383

Abstract: Methods, systems, apparatus, and articles of manufacture to cool integrated circuit packages having glass substrates are disclosed. An example glass core of an integrated circuit (IC) package disclosed herein includes a fluid inlet to receive a cooling fluid, a fluid outlet, and a channel to fluidly couple the fluid inlet to the fluid outlet, the cooling fluid to flow through the channel from the fluid inlet to the fluid outlet, the channel fluidly isolated from one or more vias extending between a first surface and a second surface of the glass core.

公开(公告)号：US20240213026A1

公开(公告)日：2024-06-27

申请号：US18085768

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Matthew J. Prince ,  Lawrence Zaino ,  Barry B. Butler ,  Girish Sharma ,  Robert R. Mitchell ,  Rajaram A. Pai ,  Niels Sveum ,  Alison V. Davis ,  Chun Chen Kuo ,  Reza Bayati ,  Swapnadip Ghosh

IPC: H01L21/28 ,  B24B37/04 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  B24B37/04 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Techniques are provided herein to form semiconductor devices that include a gate cut formed after the formation of source or drain contacts and with a top surface that is substantially coplanar with a top surface of the source or drain contacts. An example semiconductor device includes a gate structure around or otherwise on a semiconductor region and a dielectric layer present on a top surface of the gate structure. Conductive contacts are formed over source and drain regions along a source/drain contact recess or trench. The gate structure may be interrupted with a gate cut that extends through an entire thickness of the gate structure and includes a dielectric material. A top surface of the gate cut may be polished until it is substantially coplanar with a top surface of the dielectric layer over the gate structure and a top surface of the source or drain contacts.

公开(公告)号：US20240212098A1

公开(公告)日：2024-06-27

申请号：US18146927

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Niloufar Pourian

IPC: G06T5/00

CPC classification number: G06T5/00 ,  G06T2207/10016 ,  G06T2207/20084

Abstract: This disclosure describes systems, methods, and devices related to video background matte generation. A method may include receiving, by a first neural network trained to generate alpha mattes and foreground multi-camera images, first inputs generated by a second neural network; receiving, by the first neural network, second inputs comprising grayscale images and depth maps of the multi-camera images; and generating, by the first neural network, based on the first inputs and the second inputs, multi-view alpha mattes and multi-view foreground estimates for the multi-camera images.

公开(公告)号：US20240211549A1

公开(公告)日：2024-06-27

申请号：US18591640

申请日：2024-02-29

Applicant: Intel Corporation

Inventor： Marius Arvinte ,  Brandon Edwards ,  Cory Cornelius ,  Jason Martin ,  Sebastian Szyller ,  Micah Sheller ,  Nageen Himayat

IPC: G06F21/10

CPC classification number: G06F21/101

Abstract: An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to access a first set of samples associated with a diffusion model, the first set of samples including a plurality of input data samples, generate a representation of the first set of samples, sample the representation of the first set of samples to generate a representation of a second set of samples, and generate the second set of samples from the representation of the second set of samples, the second set of samples including a plurality of output data samples, an output data sample corresponding to an input data sample and being different from the corresponding input data sample.