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    Integrated circuit memory devices having selectable column addressing and methods of operating same
    72.
    发明授权
    Integrated circuit memory devices having selectable column addressing and methods of operating same 失效
    具有可选择列寻址的集成电路存储器件及其操作方法

    公开(公告)号：US06438063B1

    公开(公告)日：2002-08-20

    申请号：US09714302

    申请日：2000-11-16

    Applicant: Ho-Cheol Lee

    Inventor： Ho-Cheol Lee

    IPC: G06F1206

    CPC classification number: G11C7/225 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C2207/2281

    Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平是第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的去激活信号，使得响应于激活信号的所选存储器组在活动周期中工作，而未被选择的存储器组响应于 灭活信号在预充电循环中工作。

    Synchronous semiconductor memory device with a write latency control function
    73.
    发明授权
    Synchronous semiconductor memory device with a write latency control function 失效
    具有写延迟控制功能的同步半导体存储器件

    公开(公告)号：US5568445A

    公开(公告)日：1996-10-22

    申请号：US397690

    申请日：1995-03-02

    Applicant: Churoo Park ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Hyun-Soon Jang

    Inventor： Churoo Park ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Hyun-Soon Jang

    IPC: G11C11/407 ,  G11C7/00 ,  G11C7/22 ,  G11C11/408 ,  G11C8/00

    CPC classification number: G11C7/22

    Abstract: A semiconductor memory device for processing data in synchronization with a system clock applied from the exterior includes a circuit for generating a write latency control signal, a circuit for generating one active information enlarged signal from a plurality of active information signals generated in response to a column related control signal supplied from the exterior, and a circuit for holding internal operations of a column address counter, a burst length counter and a data transfer switching circuit for a prescribed time in which the active information enlarged signal is in an active state.

    Abstract translation: 一种用于与从外部施加的系统时钟同步地处理数据的半导体存储器件包括用于产生写等待时间控制信号的电路，用于根据响应于列产生的多个有效信息信号产生一个有源信息放大信号的电路 以及用于保持列地址计数器，脉冲串长度计数器和数据传输切换电路的内部操作的电路，其中有效信息放大信号处于活动状态的规定时间。

    Data output buffer of a synchronous semiconductor memory device
    74.
    发明授权
    Data output buffer of a synchronous semiconductor memory device 失效
    同步半导体存储器件的数据输出缓冲器

    公开(公告)号：US5384750A

    公开(公告)日：1995-01-24

    申请号：US130130

    申请日：1993-10-04

    Applicant: Ho-cheol Lee

    Inventor： Ho-cheol Lee

    IPC: H01L27/10 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  G11C8/00

    CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/22

    Abstract: A data output buffer is used for a synchronous semiconductor memory device carrying out a data read/write operation in synchronism with an externally supplied clock. The semiconductor memory device includes a first shift register having a plurality of clock stages for transmitting a RAS signal in response to the clock; a circuit for extracting a data output margin signal from a predetermined stage among the stages of the first shift circuit; first latch circuits each receiving the data output margin signal, for generating a plurality of first latency signals having information on the RAS signal by combining row address signals and the signals extracted from the respective clock stages of the first shift circuit; a second shift circuit having a plurality of clock stages for transmitting a CAS signal in response to the clock; second latch circuits each receiving the data output margin signal, for generating a plurality of second latency signals having information on the CAS signal by combining column address signals and the signals extracted from the respective clock stages of the second shift circuit; and a latency combination circuit receiving the first and second latency signals, for generating a data output control signal to the data output buffer, so that the data output buffer can generate data output even during a RAS precharge cycle.

    Abstract translation: 数据输出缓冲器用于与外部提供的时钟同步地执行数据读/写操作的同步半导体存储器件。 半导体存储器件包括具有多个时钟级的第一移位寄存器，用于响应于时钟传输＆amp; R和R信号; 用于从第一移位电路的各级中的预定级提取数据输出余量信号的电路; 每个接收数据输出余量信号的第一锁存电路，用于通过组合行地址信号和从第一移位电路的各个时钟级提取的信号来产生具有关于＆upbar＆R信号的信息的多个第一等待时间信号; 具有多个时钟级的第二移位电路，用于响应于所述时钟发送＆upbar＆C信号; 每个接收数据输出余量信号的第二锁存电路，用于通过组合列地址信号和从第二移位电路的各个时钟级提取的信号来生成具有关于CAS信号的信息的多个第二等待时间信号; 以及延迟组合电路，其接收第一和第二等待时间信号，用于产生到数据输出缓冲器的数据输出控制信号，使得数据输出缓冲器甚至可以在＆lt;上拉和预充电循环期间产生数据输出。

    Method controlling deep power down mode in multi-port semiconductor memory
    77.
    发明授权
    Method controlling deep power down mode in multi-port semiconductor memory 有权
    在多端口半导体存储器中控制深度掉电模式的方法

    公开(公告)号：US08391095B2

    公开(公告)日：2013-03-05

    申请号：US12768060

    申请日：2010-04-27

    Applicant: Ho-Cheol Lee ,  Jung-Bae Lee

    Inventor： Ho-Cheol Lee ,  Jung-Bae Lee

    IPC: G11C5/14

    CPC classification number: G11C5/148 ,  G11C5/144 ,  G11C5/147 ,  G11C8/16

    Abstract: Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.

    Abstract translation: 公开了一种在多端口半导体存储器中控制深度掉电模式的方法，该多端口半导体存储器具有连接到多个处理器的多个端口。 执行多端口半导体存储器中的深度掉电模式的控制，使得根据通过多个端口中的各个端口施加的信号来确定深度掉电模式的激活/去激活。

    Semiconductor memory device and memory system having the same
    78.
    发明授权
    Semiconductor memory device and memory system having the same 有权
    半导体存储器件和具有该半导体存储器件的存储器系统

    公开(公告)号：US08154934B2

    公开(公告)日：2012-04-10

    申请号：US12788029

    申请日：2010-05-26

    Applicant: Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

    Inventor： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

    IPC: G11C7/00 ,  G11C8/18

    CPC classification number: G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

    Abstract: A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.

    Abstract translation: 公开了一种半导体存储器件。 半导体器件包括存储单元阵列，时钟信号发生器，被配置为从存储器件的外部接收外部时钟信号并输出​​内部时钟信号;以及数据输出单元，被配置为从存储器单元接收内部数据信号 阵列并响应于内部时钟信号输出读取数据信号。 半导体存储器件还包括读取数据选通单元，其被配置为基于内部时钟信号的周期时间，输出具有n倍（n是等于或大于2的整数）的周期时间的读取数据选通信号 内部时钟信号。

    STACKED MEMORY DEVICE HAVING INTER-CHIP CONNECTION UNIT, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF COMPENSATING FOR DELAY TIME OF TRANSMISSION LINE
    79.
    发明申请
    STACKED MEMORY DEVICE HAVING INTER-CHIP CONNECTION UNIT, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF COMPENSATING FOR DELAY TIME OF TRANSMISSION LINE 有权
    具有片间连接单元的堆叠存储器件，包括其的存储器系统以及传输线延迟时间补偿方法

    公开(公告)号：US20110249483A1

    公开(公告)日：2011-10-13

    申请号：US13080061

    申请日：2011-04-05

    Applicant: Chi-Sung Oh ,  Jin-Ho Kim ,  Ho-Cheol Lee ,  Uk-Song Kang ,  Hoon Lee

    Inventor： Chi-Sung Oh ,  Jin-Ho Kim ,  Ho-Cheol Lee ,  Uk-Song Kang ,  Hoon Lee

    IPC: G11C5/06 ,  G11C7/00

    CPC classification number: G11C7/10 ,  G11C5/02 ,  G11C7/1048

    Abstract: A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.

    Abstract translation: 提供一种叠层半导体存储器件，其包括第一存储器芯片，该第一存储器芯片包括第一传输线，第二传输线和被配置为对第一传输线的第一信号执行逻辑运算的逻辑电路和第二传输线的第二信号 传输线。 层叠半导体存储器件还包括堆叠在第一存储器芯片上的第二存储器芯片，电连接在第二存储器芯片和第一存储器芯片的第一传输线之间的芯片间连接单元，以及虚拟芯片间连接单元 电耦合到第一存储器芯片的第二传输线并且与第二存储器芯片电隔离。

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