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    Wiring structure of semiconductor device and production method of the device
    71.
    发明申请
    Wiring structure of semiconductor device and production method of the device 有权
    半导体器件的接线结构及器件的制造方法

    公开(公告)号：US20050087871A1

    公开(公告)日：2005-04-28

    申请号：US10760457

    申请日：2004-01-21

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L29/40

    CPC classification number: H01L23/53295 ,  H01L21/2885 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a wiring structure of a semiconductor device, dielectric tolerance of the wiring is improved by preventing diffusion of the wiring material. The wiring structure of the semiconductor device includes a first insulating film having plural grooves, plural wiring films formed protrusively above tops of the first insulating film among the grooves, plural barrier films formed on bottoms of the wiring films and up to a higher position than the tops on sides of the wiring films, first cap films comprising metal films formed on tops of the wiring films, and a second cap film formed on at least respective sides of the first cap films and the barrier films.

    Abstract translation: 在半导体器件的布线结构中，通过防止布线材料的扩散，提高布线的电介质公差。 半导体器件的布线结构包括具有多个沟槽的第一绝缘膜，多个布线膜，突出地形成在沟槽中的第一绝缘膜的顶部之上，多个阻挡膜形成在布线膜的底部上方，高于 布线膜侧面的顶部，包含形成在布线膜的顶部的金属膜的第一盖膜，以及形成在第一盖膜和阻挡膜的至少两侧的第二盖膜。

    Method for manufacturing an infrared detection element
    72.
    发明申请
    Method for manufacturing an infrared detection element 审中-公开
    红外线检测元件的制造方法

    公开(公告)号：US20050006584A1

    公开(公告)日：2005-01-13

    申请号：US10901110

    申请日：2004-07-29

    Applicant: Takashi Kawakubo ,  Kazuhide Abe ,  Kenya Sano

    Inventor： Takashi Kawakubo ,  Kazuhide Abe ,  Kenya Sano

    IPC: G01J1/02 ,  G01J5/02 ,  G01J5/34 ,  H01L37/02 ,  G01J5/10 ,  H01L37/00

    CPC classification number: H01L37/02

    Abstract: The present invention provides an infrared detection element having a single-crystalline base layer 3 with a thickness of 50 nm to 10 μm having a principal surface, a first electrode layer 4 formed on the principal surface of the single-crystalline base layer 3, a ferroelectric layer 5 which is formed on the first electrode layer 4 and is composed of a single-crystalline layer or a unidirectioally oriented layer. Distortion of the single-crystalline layer or a unidirectioally oriented layer in a surface parallel to the principal surface of the single-crystalline base layer 3 is elastically constrained by the single-crystalline base layer 3. The infrared detection element further has a second electrode layer 6 formed on the ferroelectric layer 5. An amount of charge is changed by changes in temperature caused by irradiation of infrared light to the ferroelectric layer 5. The amount of the charge is detected from the first and the second electrode layer4, 6. With the infrared detection element, an accurate temperature measurement is possible even in the neighborhood of the Curie temperature due to a discontinuous primary phase transition.

    Abstract translation: 本发明提供一种红外线检测元件，其具有厚度为50nm〜10μm的具有主面的单晶基底层3，形成在单晶基底层3的主面上的第一电极层4， 形成在第一电极层4上并由单晶层或单向取向层构成的铁电体层5。 在与单晶基底层3的主表面平行的表面中的单晶层或单向取向层的失真由单晶基底层3弹性约束。红外线检测元件还具有第二电极层 形成在铁电层5上的电荷量。由于红外光照射到铁电层5而引起的温度变化，电荷量被改变。从第一和第二电极层4,6检测电荷量。 红外线检测元件，由于不连续的初级相变，即使在居里温度附近也可进行精确的温度测量。

    Method of forming embedded wiring in a groove in an insulating layer
    74.
    发明授权
    Method of forming embedded wiring in a groove in an insulating layer 有权
    在绝缘层的槽中形成嵌入布线的方法

    公开(公告)号：US06498098B1

    公开(公告)日：2002-12-24

    申请号：US09625505

    申请日：2000-07-26

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L214763

    CPC classification number: H01L21/76846 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76877

    Abstract: According to the present invention, a semiconductor device is fabricated by: forming an insulation layer on a substrate; forming a groove in the surface of the insulation layer; forming a diffusion protection layer on the surface of the insulation layer including inside of the groove; forming a reaction layer on the diffusion protection layer; forming an oxide layer on the surface of the reaction layer; forming a layer of a wiring material on the oxide layer to embed the groove; forming a layer of a mixture of the reaction layer, the layer of the wiring material and the oxide layer by annealing; and removing the diffusion protection layer, the mixture layer and the layer of the wiring material from the surface of the insulation layer except for the diffusion protection layer, the mixture layer and the layer of the wiring material in the groove. By this fabrication method, the reaction of the wiring material such as copper and the underlying metal can be suppressed, thus suppressing the reduction in the cross-sectional size of the wiring material.

    Abstract translation: 根据本发明，通过在基板上形成绝缘层来制造半导体器件; 在绝缘层的表面上形成凹槽; 在包括槽内部的绝缘层的表面上形成扩散保护层; 在扩散保护层上形成反应层; 在反应层的表面上形成氧化物层; 在所述氧化物层上形成布线材料层以嵌入所述沟槽; 通过退火形成反应层，布线材料层和氧化物层的混合物层; 除了漫射保护层，混合层和布线材料层中的绝缘层的表面之外，从沟槽中除去扩散保护层，混合层和布线材料层。 通过该制造方法，可以抑制诸如铜和下面的金属之类的布线材料的反应，从而抑制布线材料的横截面尺寸的减小。

    Semiconductor memory device using ferroelectric capacitor and having only one sense amplifier selected
    76.
    发明授权
    Semiconductor memory device using ferroelectric capacitor and having only one sense amplifier selected 失效
    使用铁电电容器并且仅选择一个读出放大器的半导体存储器件

    公开(公告)号：US5400275A

    公开(公告)日：1995-03-21

    申请号：US712092

    申请日：1991-06-07

    Applicant: Kazuhide Abe ,  Hiroshi Toyoda ,  Koji Yamakawa ,  Motomasa Imai ,  Koji Sakui

    Inventor： Kazuhide Abe ,  Hiroshi Toyoda ,  Koji Yamakawa ,  Motomasa Imai ,  Koji Sakui

    IPC: G11C11/22 ,  H01L27/115 ,  G11C7/00

    CPC classification number: H01L27/11502 ,  G11C11/22

    Abstract: A semiconductor memory device comprises a plurality of memory cells arranged in the form of a matrix to constitute rows-and columns, a plurality of first driving lines, connected to the memory cells, for transmitting a first driving signal to the memory cells, one of the plurality of first driving lines being selected by a row address, a plurality of second driving lines, connected to the memory cells, for transmitting a second driving signal to the memory cells, one of the plurality of second driving lines being selected by a column address, a plurality of read/write lines, connected to the memory cells, for performing read/write operations with respect to the memory cells, and a plurality of sense amplifiers connected to the read/ write lines, wherein one of the plurality of sense amplifiers is selected by the column address, and the memory cells in the same column are connected to the same sense amplifier through the read/write lines.

    Abstract translation: 一种半导体存储器件包括以矩阵形式布置以构成行和列的多个存储器单元，连接到存储器单元的多条第一驱动线，用于将第一驱动信号发送到存储器单元，其中之一 所述多个第一驱动线由行地址选择，多个第二驱动线连接到所述存储单元，用于将第二驱动信号发送到所述存储单元，所述多个第二驱动线中的一个由列选择 连接到存储器单元的多个读/写线，用于对存储单元执行读/写操作，以及连接到读/写线的多个读出放大器，其中多个感测中的一个 放大器由列地址选择，同一列中的存储单元通过读/写线连接到相同的读出放大器。

    Acoustic semiconductor device
    78.
    发明授权
    Acoustic semiconductor device 失效
    声学半导体器件

    公开(公告)号：US08648431B2

    公开(公告)日：2014-02-11

    申请号：US13220116

    申请日：2011-08-29

    Applicant: Kazuhide Abe ,  Tadahiro Sasaki ,  Atsuko Iida ,  Kazuhiko Itaya ,  Takashi Kawakubo

    Inventor： Kazuhide Abe ,  Tadahiro Sasaki ,  Atsuko Iida ,  Kazuhiko Itaya ,  Takashi Kawakubo

    IPC: H01L29/84

    CPC classification number: H03J3/20 ,  H03B5/326 ,  H03H9/02566

    Abstract: According to one embodiment, an acoustic semiconductor device includes an element unit, and a first terminal. The element unit includes an acoustic resonance unit. The acoustic resonance unit includes a semiconductor crystal. An acoustic standing wave is excitable in the acoustic resonance unit and is configured to be synchronously coupled with electric charge density within at least one portion of the semiconductor crystal via deformation-potential coupling effect. The first terminal is electrically connected to the element unit. At least one selected from outputting and inputting an electrical signal is implementable via the first terminal. The electrical signal is coupled with the electric charge density. The outputting the electrical signal is from the acoustic resonance unit, and the inputting the electrical signal is into the acoustic resonance unit.

    Abstract translation: 根据一个实施例，声学半导体器件包括元件单元和第一端子。 元件单元包括声共振单元。 声共振单元包括半导体晶体。 声驻波在声共振单元中是可兴奋的，并且被配置为通过变形电势耦合效应与半导体晶体的至少一部分内的电荷密度同步耦合。 第一端子电连接到元件单元。 从输出和输入电信号中选出的至少一个可经由第一终端实现。 电信号与电荷密度耦合。 输出电信号来自声共振单元，并且输入电信号进入声共振单元。

    Power amplifier
    80.
    发明授权
    Power amplifier 失效
    功率放大器

    公开(公告)号：US08324707B2

    公开(公告)日：2012-12-04

    申请号：US13050545

    申请日：2011-03-17

    Applicant: Tadahiro Sasaki ,  Kazuhide Abe ,  Atsuko Iida ,  Kazuhiko Itaya

    Inventor： Tadahiro Sasaki ,  Kazuhide Abe ,  Atsuko Iida ,  Kazuhiko Itaya

    IPC: H01L27/105

    CPC classification number: H01L27/088 ,  H01L21/823493 ,  H01L27/0207 ,  H01L27/0922 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/78

    Abstract: According to an embodiment, a power amplifier is provided with at least one first growth ring gate structure and multiple second growth ring gate structures. The first growth ring gate structure is bounded by a semiconductor layer and performs a power amplification operation. The multiple second growth ring gate structures are bounded by the semiconductor layer and are arranged adjacently around the first growth ring gate structure in a surrounding manner. When the first growth ring gate structure performs a power amplification operation, the multiple second growth ring gate structures are depleted by applying a reverse bias to the multiple second growth ring gate structures whereby the depleted multiple second growth ring gate structures isolate the first growth ring gate structure from a surrounding portion.

    Abstract translation: 根据实施例，功率放大器设置有至少一个第一增长环栅极结构和多个第二增长环栅极结构。 第一生长环栅极结构由半导体层限制并进行功率放大操作。 多个第二生长环形栅极结构由半导体层限制，并且以周围的方式围绕第一生长环栅极结构相邻布置。 当第一生长环栅极结构执行功率放大操作时，通过向多个第二生长环栅极结构施加反向偏压来耗尽多个第二生长环栅结构，由此耗尽的多个第二生长环栅极结构将第一生长环栅极隔离 结构从周围部分。

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