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    Digital camera module using stacked chip package
    72.
    发明申请
    Digital camera module using stacked chip package 有权
    数码相机模块采用堆叠芯片封装

    公开(公告)号：US20070165136A1

    公开(公告)日：2007-07-19

    申请号：US11592912

    申请日：2006-11-03

    Applicant: Ying-Cheng Wu ,  Ying-Tang Su

    Inventor： Ying-Cheng Wu ,  Ying-Tang Su

    IPC: H04N5/225

    CPC classification number: H04N5/2253 ,  H01L2224/48091 ,  H01L2224/8592 ,  H01L2924/16195 ,  H04N5/2254 ,  H04N5/2257 ,  H01L2924/00014

    Abstract: A digital camera module (10) includes a chip package (101) and a lens module (103) mounted on the chip package. The chip package includes a substrate (20), a first chip (40), a second chip (70), and a cover (80). The first chip is mounted on the substrate and is electrically connected with the substrate via a first plurality of wires (50a). The second chip is mounted above the first chip and above the wires connected with the first chip and is electrically connected with the substrate via a second plurality of wires (50b). The cover is mounted above the second chip and the wires connected with the second chip.

    Abstract translation: 数字照相机模块（10）包括芯片封装（101）和安装在芯片封装上的透镜模块（103）。 芯片封装包括基板（20），第一芯片（40），第二芯片（70）和盖（80）。 第一芯片安装在基板上，并通过第一多根导线（50a）与基板电连接。 第二芯片安装在第一芯片上方并且连接在与第一芯片连接的导线上方，并且经由第二多个导线（50b）与基板电连接。 盖被安装在第二芯片上方，并且电线与第二芯片连接。

    Stacked chip packaging structure
    73.
    发明申请
    Stacked chip packaging structure 审中-公开
    堆叠芯片封装结构

    公开(公告)号：US20070152345A1

    公开(公告)日：2007-07-05

    申请号：US11592848

    申请日：2006-11-03

    Applicant: Ying-Cheng Wu ,  Ying-Tang Su

    Inventor： Ying-Cheng Wu ,  Ying-Tang Su

    IPC: H01L23/52

    CPC classification number: H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48992 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/00014

    Abstract: A stacked chip packaging structure (10) includes a substrate (20), a first chip (40), a second chip (70), and a cover (80). The first chip is mounted on the substrate and is electrically connected with the substrate via a first plurality of wires (50a). The second chip is mounted above the first chip and above the wires connected with the first chip and is electrically connected with the substrate via a second plurality of wires (50b). The cover is mounted above the second chip and the wires connected with the second chip. The mounting of the second chip and the cover in such a manner is facilitated through the use of an adhesive/glue (60a, 60b) that is able to function both as an adherent and as a spacer.

    Abstract translation: 堆叠式芯片封装结构（10）包括基板（20），第一芯片（40），第二芯片（70）和盖（80）。 第一芯片安装在基板上，并通过第一多根导线（50a）与基板电连接。 第二芯片安装在第一芯片上方并且连接在与第一芯片连接的导线上方，并且经由第二多个导线（50b）与基板电连接。 盖被安装在第二芯片上方，并且电线与第二芯片连接。 通过使用能够既作为粘着剂又作为隔离物使用的粘合剂/胶（60a，60b），可以有利于以这种方式安装第二芯片和盖。

    Image sensor chip package fabrication method
    75.
    发明申请
    Image sensor chip package fabrication method 有权
    图像传感器芯片封装制造方法

    公开(公告)号：US20070057149A1

    公开(公告)日：2007-03-15

    申请号：US11453456

    申请日：2006-06-14

    Applicant: Steven Webster ,  Ying-Cheng Wu ,  Kun-Hsieh Liu

    Inventor： Steven Webster ,  Ying-Cheng Wu ,  Kun-Hsieh Liu

    IPC: H01L27/00

    CPC classification number: H01L27/14685 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14683 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014

    Abstract: An image sensor package method includes the steps of first, providing a carrier (30), which includes a base (24) and a leadframe (320). The base has a cavity therein and the leadframe includes a number of conductive pieces; Second, mounting an image sensor chip on the base and received in the cavity, the image sensor having a photosensitive area. Third, providing a plurality of wires, each electrically connects the image sensor chip and a corresponding one of the conductive pieces of the carrier. Fourth, applying an adhesive means around the image sensor chip that at least partially covers all the wires. Finally, mounting a transparent cover on the carrier, where an adhesive means fixes the cover in place.

    Abstract translation: 图像传感器封装方法包括以下步骤：首先提供一种包括基座（24）和引线框架（320）的载体（30）。 基座在其中具有空腔，引线框架包括多个导电件; 第二，将图像传感器芯片安装在基座上并被接纳在空腔中，图像传感器具有感光区域。 第三，提供多条导线，每个电线将图像传感器芯片和载体的相应的一个导电片电连接。 第四，在图像传感器芯片周围施加至少部分地覆盖所有电线的粘合剂装置。 最后，将透明盖子安装在托架上，粘合剂将盖子固定在适当位置。

    Image sensor chip package
    76.
    发明申请
    Image sensor chip package 审中-公开
    图像传感器芯片封装

    公开(公告)号：US20070034772A1

    公开(公告)日：2007-02-15

    申请号：US11448314

    申请日：2006-06-07

    Applicant: Steven Webster ,  Ying-Cheng Wu

    Inventor： Steven Webster ,  Ying-Cheng Wu

    IPC: C12Q1/68

    CPC classification number: H04N5/2253 ,  H01L2224/32014 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/16195 ,  H01L2924/00014

    Abstract: A digital camera module includes a barrel (10), a seat (20) and an image sensor chip package (30) in accordance with a preferred embodiment is shown. The image sensor chip package includes a carrier (32), a chip (34), a number of bonding wires (36) and a cover (38). The carrier includes a base (24). The chip is mounted on the base and has an active area. The second conductive means electronically connects the chip and the conductive means. An adhesive means is applied around the active area of the chip. The transparent cover is mounted to the base of the carrier. The cover adheres to the carrier with the adhesive means and defines a sealing space (37) for sealing the active area of the chip therein. The active area of the chip is sufficiently protected from pollution by the small volume of the sealing space.

    Abstract translation: 示出了根据优选实施例的数字照相机模块，包括镜筒（10），座（20）和图像传感器芯片封装（30）。 图像传感器芯片封装包括载体（32），芯片（34），多个接合线（36）和盖（38）。 载体包括基部（24）。 芯片安装在基座上并具有有效区域。 第二导电装置电连接芯片和导电装置。 在芯片的有效区域周围施加粘合剂。 透明盖安装在托架的底座上。 盖子用粘合剂粘合到载体上并且限定用于密封芯片的有效区域的密封空间（37）。 芯片的有效面积被充分保护，免受小体积密封空间的污染。

    Image sensor chip package
    77.
    发明申请
    Image sensor chip package 失效
    图像传感器芯片封装

    公开(公告)号：US20070023608A1

    公开(公告)日：2007-02-01

    申请号：US11448570

    申请日：2006-06-07

    Applicant: Steven Webster ,  Ying-Cheng Wu

    Inventor： Steven Webster ,  Ying-Cheng Wu

    IPC: C12Q1/68

    CPC classification number: H01L27/14618 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2224/32014 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/16195 ,  H01L2924/00014

    Abstract: A chip package (200) includes a carrier (20), a chip (22), a second conductive means (26) and a transparent cover (28). The carrier (20) includes a base (24). The chip is mounted on the base and has an active area (222). The second conductive means electronically connects the chip with the conductive means. The first adhesive means is applied around the active area of the chip. The transparent cover is mounted to the base of the carrier. The cover is adhered with the first adhesive means so as to define a sealing space (32) for sealing the active area of the chip therein. It can be seen that the active area of the chip is sufficiently protected from pollution by the small volume of the sealing space.

    Abstract translation: 芯片封装（200）包括载体（20），芯片（22），第二导电装置（26）和透明盖（28）。 载体（20）包括基座（24）。 芯片安装在基座上并具有有效区域（222）。 第二导电装置将芯片与导电装置电连接。 第一粘合装置被施加在芯片的有效区域周围。 透明盖安装在托架的底座上。 该盖用第一粘合装置粘合以便限定用于密封芯片的有效区域的密封空间（32）。 可以看出，芯片的有效面积被充分保护，免受小体积密封空间的污染。

    Multi-bit stacked-type non-volatile memory and manufacture method thereof
    79.
    发明申请
    Multi-bit stacked-type non-volatile memory and manufacture method thereof 有权
    多位堆叠型非易失性存储器及其制造方法

    公开(公告)号：US20060063339A1

    公开(公告)日：2006-03-23

    申请号：US11269671

    申请日：2005-11-09

    Applicant: Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

    Inventor： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

    IPC: H01L21/331 ,  H01L21/8222

    CPC classification number: H01L21/28273 ,  H01L29/66825 ,  H01L29/7887

    Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

    Abstract translation: 本发明公开了一种具有间隔型浮动栅极的多位堆叠型非易失性存储器及其制造方法。 制造方法包括在半导体衬底上形成含有砷的图案化电介质层，其中图案化电介质层限定开口作为有效区域。 在图案化电介质层的侧壁上形成介质间隔物，并在半导体衬底上形成栅极电介质层。 源极/漏极区域通过使从扩散图案化的介电层扩散到半导体衬底中的热驱动方法形成。 间隔物形状的浮栅形成在电介质隔离物的侧壁和栅介电层上。 在间隔物形浮栅上形成层间绝缘层。 在层间电介质层上形成控制栅极，填充有源区的开口。

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