公开(公告)号：US20090050996A1

公开(公告)日：2009-02-26

申请号：US11987232

申请日：2007-11-28

Applicant: Chien-Hung Liu ,  Sih-Dian Lee

Inventor： Chien-Hung Liu ,  Sih-Dian Lee

IPC: H01L31/0203 ,  H01L31/18 ,  H01L21/58 ,  H01L23/15

CPC classification number: H01L31/0203 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/13 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14687 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/00

Abstract: Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

Abstract translation: 电子装置晶圆级规包装及其制造方法。 提供了形成有多个电子器件的半导体晶片。 半导体晶片与支撑基板结合。 半导体衬底的背面变薄。 通过蚀刻暴露层间电介质层的半导体形成第一沟槽。 绝缘层顺应地沉积在半导体衬底的背面上。 去除第一沟槽底部的绝缘层以产生第二沟槽。 依次去除绝缘层和ILD层，暴露一对接触焊盘的一部分。 导电层顺应地形成在半导体的背面上。 导电层被图案化之后，导电层和接触垫构成S形连接。 接下来，随后形成外部连接和端子接触焊盘。

公开(公告)号：US20080182355A1

公开(公告)日：2008-07-31

申请号：US11657734

申请日：2007-01-25

Applicant: Chien-Hung Liu

Inventor： Chien-Hung Liu

IPC: H01L21/00 ,  H01L31/0203

CPC classification number: H01L27/14618 ,  H01L24/16 ,  H01L25/042 ,  H01L27/14683 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A conducting layer in a chip package module includes one or a plurality of through hole penetrating the top of a base being disposed at the bottom of an insulating layer in the chip package module, and inner wall of the through hole being applied with insulation material so that the conductive layer subsequently constructed to the peripheral of the insulation layer may pass the through hole to extend to where above the base before construction of a masking layer and multiple circuit pins to complete construction of the conducting layer that is totally enveloped so to prevent easy oxidization at the conducting layer and improve stability of the chip package to avoid breaking up due to external force applied.

Abstract translation: 芯片封装模块中的导电层包括穿过基片顶部的一个或多个通孔，其设置在芯片封装模块中的绝缘层的底部，并且通孔的内壁被施加绝缘材料 随后构造到绝缘层的周边的导电层可以在构造掩模层和多个电路引脚之前通过通孔延伸到基底之上，以完成包封的导电层的构造，从而防止容易 导电层氧化，提高芯片封装的稳定性，避免施加外力而导致断裂。

公开(公告)号：US07299016B2

公开(公告)日：2007-11-20

申请号：US11329245

申请日：2006-01-11

Applicant: Chien-Hung Liu

Inventor： Chien-Hung Liu

IPC: H01Q11/12

CPC classification number: G09G3/3406 ,  G09G2320/0606 ,  G09G2320/0626 ,  H04M1/22 ,  H04W52/027 ,  Y02D70/00

Abstract: The present invention discloses a communication device with an adjustable brightness that includes a control circuit coupled to a modulating unit, and the modulating unit includes a tuning button disposed on the communication device that allows user to make adjustments or controls by the tuning button to produce a first set value, and the modulating unit converts the power received by a power supply circuit of the communication device into a corresponding operating voltage according to the first set value and sends the operating voltage to a light emitting unit of the communication device for projecting a light source according to the magnitude of the operating voltage, so as to adjust and change the brightness of the light emitting unit, and achieve the effects of saving power and extending the life of the light emitting units.

Abstract translation: 本发明公开了一种具有可调节亮度的通信设备，其包括耦合到调制单元的控制电路，并且调制单元包括设置在通信设备上的调谐按钮，其允许用户通过调谐按钮进行调节或控制以产生 第一设定值，并且调制单元根据第一设定值将由通信设备的电源电路接收的功率转换为相应的工作电压，并将工作电压发送到用于投射光的通信设备的发光单元 源，根据工作电压的大小，调整和改变发光单元的亮度，并实现节能和延长发光单元寿命的效果。

公开(公告)号：US20050142871A1

公开(公告)日：2005-06-30

申请号：US10819137

申请日：2004-04-07

Applicant: Chien-Hung Liu ,  Ming-Huan Yang ,  Jane Chang ,  Chun-Jung Chen ,  Chao-Kai Cheng ,  Kou-Chen Liu

Inventor： Chien-Hung Liu ,  Ming-Huan Yang ,  Jane Chang ,  Chun-Jung Chen ,  Chao-Kai Cheng ,  Kou-Chen Liu

IPC: H01L21/20 ,  H01L21/288 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/417 ,  H01L29/45 ,  H05K3/00 ,  H05K3/32 ,  H05K3/40

CPC classification number: H01L29/66742 ,  H01L21/288 ,  H01L21/76802 ,  H01L21/76838 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66765 ,  H05K3/002 ,  H05K3/4069 ,  H05K2203/013 ,  H05K2203/0783

Abstract: A method of forming a conductive via plug is disclosed. The conductive via plug is formed by printing a solution comprising a solvent with insulating material dissolve capability and a conductive material by an inkjet method. The formed conductive via plug has a low resistivity and thus may serve as an electrical connection between two separate conductive layers. This manufacturing method of the conductive via plug may achieve simultaneously deposition, patterning and etching purposes, which significantly simplifies the manufacturing process.

Abstract translation: 公开了形成导电通孔的方法。 导电通孔插塞是通过用喷墨法印刷包含具有绝缘材料溶剂的溶剂的溶液和导电材料而形成的。 所形成的导电通孔塞具有低电阻率，因此可以用作两个分开的导电层之间的电连接。 导电通孔插头的这种制造方法可以实现同时沉积，图案化和蚀刻目的，这显着简化了制造工艺。

公开(公告)号：US20050006694A1

公开(公告)日：2005-01-13

申请号：US10682861

申请日：2003-10-14

Applicant: Chien-Hung Liu

Inventor： Chien-Hung Liu

IPC: H01L21/8246 ,  H01L27/115 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7923

Abstract: A NAND type dual bit nitride read only memory and a method for fabricating thereof are provided. Firstly, a plurality of isolation layers, which are spaced and parallel to each other are formed in the substrate. Next, a plurality of word lines and a plurality of oxide-nitride-oxide (ONO) stack structures are formed on the substrate. The word lines are spaced and parallel to each other, and also the word lines are perpendicular to the isolation layers. Each of the ONO stack structure is located between the corresponding word line and the substrate. And then a plurality of discontinuous bit lines, which are located between the word lines and between the isolation layers are formed on the substrate. The structure of the present invention of the NAND type dual bit nitride read only memory is similar to that of a complementary metal-oxide semiconductor (CMOS), and their fabrication processes are fully compatible.

Abstract translation: 提供NAND型双位氮化物只读存储器及其制造方法。 首先，在衬底中形成彼此间隔开并平行的多个隔离层。 接下来，在基板上形成多个字线和多个氧化物 - 氮化物 - 氧化物（ONO）堆叠结构。 字线彼此间隔开并平行，字线也垂直于隔离层。 每个ONO堆叠结构位于相应的字线和基板之间。 然后，在基板上形成位于字线之间和隔离层之间的多个不连续位线。 本发明的NAND型双位氮化物只读存储器的结构类似于互补金属氧化物半导体（CMOS）的结构，并且它们的制造工艺是完全兼容的。

公开(公告)号：US06841830B2

公开(公告)日：2005-01-11

申请号：US10627637

申请日：2003-07-28

Applicant: Chien-Hung Liu ,  Jian-Chiun Liou ,  Chun-Jung Chen ,  Je-Ping Hu

Inventor： Chien-Hung Liu ,  Jian-Chiun Liou ,  Chun-Jung Chen ,  Je-Ping Hu

IPC: B41J2/14 ,  H01L21/324 ,  H01L27/06 ,  H01L29/78 ,  H01L29/76 ,  G01R19/00

CPC classification number: H01L29/78 ,  B41J2/14129 ,  B41J2002/14387 ,  B41J2202/13 ,  H01L21/324 ,  H01L27/0629

Abstract: A MOSFET and the method for fabricating them are disclosed to make the inkjet head chips. The MOSFET has the scaled-down junction formation for the source and drain. Using a lower temperature process and interlayer dielectric, the source and drain dopants can not be diffused deeply due to high-temperature driver-in. The contact holes of the drain are provided with plugs of refractory material to avoid spiking between the metal and silicon. This achieves the requirement of high-density devices on the print head chip.

Abstract translation: 公开了一种MOSFET及其制造方法，以制造喷墨头芯片。 MOSFET具有用于源极和漏极的按比例缩小的结形成。 使用较低温度工艺和层间电介质，源极和漏极掺杂物由于高温驱动而不能深入扩散。 漏斗的接触孔设置有耐火材料塞，以避免金属和硅之间的尖峰。 这实现了打印头芯片上高密度设备的要求。

公开(公告)号：US06818956B2

公开(公告)日：2004-11-16

申请号：US10643335

申请日：2003-08-15

Applicant: Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

Inventor： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC: H01L2362

CPC classification number: H01L29/792 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L29/66833

Abstract: A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer and a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

Abstract translation: 一种非易失性只读存储器件，其中字线在衬底上，字线包括金属层和多晶硅线。 捕获层还位于字线和基板之间。 多晶硅保护线形成在衬底上，多晶硅保护线连接字线和衬底中的接地掺杂区，其中多晶硅保护线的电阻高于字线的电阻。

公开(公告)号：US06680227B2

公开(公告)日：2004-01-20

申请号：US10134223

申请日：2002-04-25

Applicant: Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

Inventor： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC: H01L218238

CPC classification number: H01L29/792 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L29/66833

Abstract: A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

公开(公告)号：US06448137B1

公开(公告)日：2002-09-10

申请号：US09682941

申请日：2001-11-02

Applicant: Erh-Kun Lai ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang ,  Ying-Tso Chen

Inventor： Erh-Kun Lai ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang ,  Ying-Tso Chen

IPC: H01L218247

CPC classification number: H01L27/11568 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11573 ,  Y10S438/981

Abstract: A method of forming an NROM comprising mixed-signal circuits is provided. The method starts by providing a semiconductor substrate having a memory area and a periphery area. The periphery area has a plurality of active areas isolated by an isolation layer. A bottom electrode of a capacitor is formed atop the isolation layer in the periphery area. An ONO(oxide-nitride-oxide) process is performed. A photolithography, an anisotropic etching, and an ion implantation process are performed in order to etch the ONO dielectric layer in a bit line region not protected by the first photolithography process, and to form a plurality of buried bit lines. A photolithography and an ion implantation process are performed in order to form at least one ion well. The surface of the active area in the periphery area is wet etched. An oxidation process is performed in order to simultaneously form at least one gate oxide layer with a specific thickness in the active area, and to form a thermal oxide layer atop each of the buried bit lines in the memory area. Each of the gates, the top electrode of the capacitor and the resistor are formed in the periphery area, and a word line is formed in the memory area.

Abstract translation: 提供了一种形成包括混合信号电路的NROM的方法。 该方法通过提供具有存储区域和周边区域的半导体衬底开始。 周边区域具有由隔离层隔离的多个有效区域。 电容器的底部电极形成在外围区域中的隔离层顶部。 进行ONO（氧化物 - 氮化物 - 氧化物）处理。 执行光刻，各向异性蚀刻和离子注入工艺以蚀刻未被第一光刻工艺保护的位线区域中的ONO介电层，并形成多个掩埋位线。 进行光刻和离子注入工艺以形成至少一个离子阱。 周边区域的有源区域的表面被湿蚀刻。 执行氧化处理以在有源区域中同时形成具有特定厚度的至少一个栅极氧化物层，并且在存储区域中的每个掩埋位线上形成热氧化物层。 每个栅极，电容器的顶部电极和电阻器形成在周边区域中，并且在存储区域中形成字线。

公开(公告)号：US06436800B1

公开(公告)日：2002-08-20

申请号：US09990393

申请日：2001-11-20

Applicant: Tung-Cheng Kuo ,  Shou-Wei Hung ,  Chien-Hung Liu ,  Shyi-Shuh Pan

Inventor： Tung-Cheng Kuo ,  Shou-Wei Hung ,  Chien-Hung Liu ,  Shyi-Shuh Pan

IPC: H01L2138

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

Abstract: A fabrication method for a nonvolatile memory with a shallow junction is described. A gate structure, comprising an electron-trapping layer and a conductive layer, is formed on a substrate. A doped spacer is formed on the sidewall of the gate structure. Buried bit lines are further formed in the substrate beside the gate structure. Thereafter, thermal process is conducted to diffuse the dopants from the doped spacer into the substrate adjacent to the buried bit lines.

Abstract translation: 描述了一种具有浅结的非易失性存储器的制造方法。 在基板上形成包括电子捕获层和导电层的栅极结构。 掺杂间隔物形成在栅极结构的侧壁上。 在栅极结构旁边的衬底中进一步形成掩埋位线。 此后，进行热处理以将掺杂的掺杂剂从埋入的位线扩散到衬底中。