公开(公告)号：US20180188771A1

公开(公告)日：2018-07-05

申请号：US15398608

申请日：2017-01-04

Applicant: Intel Corporation

Inventor： Nadine L. Dabby ,  Sasha N. Oster ,  Aleksandar Aleksov ,  Braxton Lathrop ,  Racquel L. Fygenson

IPC: G06F1/16 ,  H05K3/06

CPC classification number: G06F1/163 ,  G06F1/1656 ,  H05K1/0283 ,  H05K1/038 ,  H05K3/284 ,  H05K3/321 ,  H05K3/3463 ,  H05K2201/0314 ,  H05K2203/1311 ,  H05K2203/1383

Abstract: Systems and methods describe herein provide a solution to the technical problem of creating a wearable electronic devices. In particular, these systems and methods enable electrical and mechanical attachment of stretchable or flexible electronics to fabric. A stretchable or flexible electronic platform is bonded to fabric using a double-sided fabric adhesive, and conductive adhesive is used to join pads on the electronic platform to corresponding electrical leads on the fabric. An additional waterproofing material may be used over and beneath the electronic platform to provide a water-resistant or waterproof device. This stretchable or flexible electronic platform integration process allows the platform to bend and move with the fabric while protecting the conductive connections. By using flexible and stretchable conductive leads and adhesives, the platform is more flexible and stretchable than traditional rigid electronics enclosures.

公开(公告)号：US20180096862A1

公开(公告)日：2018-04-05

申请号：US15816681

申请日：2017-11-17

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Adel A. Elsherbini ,  Joshua D. Heppner ,  Shawna M. Liff

IPC: H01L21/56 ,  H01L23/31

CPC classification number: H01L23/315 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/467 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/81

Abstract: Molded electronics package cavities are formed by placing a sacrificial material in the mold and then decomposing, washing, or etching away this sacrificial material. The electronics package that includes this sacrificial material is then overmolded, with little or no change needed in the overmolding process. Following overmolding, the sacrificial material is removed such as using a thermal, chemical, optical, or other decomposing process. This proposed use of sacrificial material allows for formation of complex 3-D cavities, and reduces or eliminates the need for precise material removal tolerances. Multiple instances of the sacrificial material may be removed simultaneously, replacing a serial drilling process with a parallel material removal manufacturing process.

公开(公告)号：US09902152B2

公开(公告)日：2018-02-27

申请号：US15199899

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Feras Eid ,  Shawna M. Liff ,  Sasha N. Oster ,  Thomas L. Sounart ,  Georgios C. Dogiamis ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: B41J2/14

CPC classification number: B41J2/14298 ,  B41J2/14201 ,  B41J2/14233 ,  B41J2002/14266 ,  B41J2202/13

Abstract: Embodiments of the invention include a piezoelectric package integrated jet device. In one example, the jet device includes a vibrating membrane positioned between first and second cavities of an organic substrate, a piezoelectric material coupled to the vibrating membrane which acts as a first electrode, and a second electrode in contact with the piezoelectric material. The vibrating membrane generates fluid flow through an orifice in response to application of an electrical signal between the first and second electrodes.

公开(公告)号：US20180026730A1

公开(公告)日：2018-01-25

申请号：US15676611

申请日：2017-08-14

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Sasha N. Oster ,  Feras Eid ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Amit Sudhir Baxi ,  Vincent S. Mageshkumar ,  Kumar Ranganathan ,  Wen-Ling M. Huang

IPC: H04B13/00 ,  A61M5/142 ,  A61B5/00 ,  A61B5/145 ,  A61N1/04 ,  A61B5/11 ,  A61B5/0402 ,  A61B5/01 ,  H04B5/00 ,  A61N7/00 ,  A61B5/021

CPC classification number: H04B13/005 ,  A61B5/0024 ,  A61B5/01 ,  A61B5/0205 ,  A61B5/021 ,  A61B5/0402 ,  A61B5/0432 ,  A61B5/1102 ,  A61B5/1107 ,  A61B5/1121 ,  A61B5/14532 ,  A61B5/14546 ,  A61B5/4839 ,  A61B5/4869 ,  A61B5/6833 ,  A61F7/007 ,  A61M5/14248 ,  A61N1/0484 ,  A61N1/0492 ,  A61N1/3603 ,  A61N7/00 ,  H04B5/0012

Abstract: Discussed generally herein are methods and devices including or providing a patch system that can help in diagnosing a medical condition and/or provide therapy to a user. A body-area network can include a plurality of communicatively coupled patches that communicate with an intermediate device. The intermediate device can provide data representative of a biological parameter monitored by the patches to proper personnel, such as for diagnosis and/or response.

公开(公告)号：US09842832B2

公开(公告)日：2017-12-12

申请号：US15183179

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC: H01L25/16 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H05K1/18

CPC classification number: H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

公开(公告)号：US20160300824A1

公开(公告)日：2016-10-13

申请号：US15183179

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

公开(公告)号：US20160197065A1

公开(公告)日：2016-07-07

申请号：US15068262

申请日：2016-03-11

Applicant: Intel Corporation

Inventor： John S. Guzek ,  Debendra Mallik ,  Sasha N. Oster ,  Timothy E. McIntosh

IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2518 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15321 ,  H01L2924/16251 ,  H01L2924/182

Abstract: Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.

公开(公告)号：US09287248B2

公开(公告)日：2016-03-15

申请号：US14104877

申请日：2013-12-12

Applicant: INTEL CORPORATION

Inventor： John S. Guzek ,  Debendra Mallik ,  Sasha N. Oster ,  Timothy E. McIntosh

IPC: H01L23/52 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2518 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15321 ,  H01L2924/16251 ,  H01L2924/182

Abstract: Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了允许诸如处理器和存储器的设备之间的相对短的连接的集成电路封装组件。 在一个实施例中，封装组件包括嵌入到直接耦合到附接到子封装的另一管芯的子封装中的管芯。 在一些实施例中，子包还可以包含电源管理装置。 在一些实施例中，嵌入在子封装和/或功率管理器件中的管芯可以与耦合到子封装的管芯定义的区域重叠或位于其中，使得它们位于耦合到子封装的管芯和衬底之间 子包。 可以描述和/或要求保护其他实施例。

公开(公告)号：US12155133B2

公开(公告)日：2024-11-26

申请号：US18133361

申请日：2023-04-11

Applicant: Intel Corporation

Inventor： Feras Eid ,  Sasha N. Oster ,  Telesphor Kamgaing ,  Georgios C. Dogiamis ,  Aleksandar Aleksov

IPC: H01Q1/38 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/522 ,  H01L23/552 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/24 ,  H01Q1/52 ,  H01Q9/04 ,  H01Q19/22 ,  H01L23/367

Abstract: Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.

公开(公告)号：US11575749B2

公开(公告)日：2023-02-07

申请号：US16757751

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Georgios C. Dogiamis ,  Sasha N. Oster ,  Adel A. Elsherbini ,  Erich N. Ewy ,  Johanna M. Swan ,  Telesphor Kamgaing

IPC: H04B1/3822 ,  H04B1/08 ,  H04L67/12 ,  B60R16/023 ,  B60R16/03 ,  G08C23/06 ,  H01P3/08 ,  H04L5/14 ,  B60W60/00

Abstract: Embodiments include a sensor node, an active sensor node, and a vehicle with a communication system that includes sensor nodes. The sensor node include a package substrate, a diplexer/combiner block on the package substrate, a transceiver communicatively coupled to the diplexer/combiner block, and a first mm-wave launcher coupled to the diplexer/combiner block. The sensor node may have a sensor communicatively coupled to the transceiver, the sensor is communicatively coupled to the transceiver by an electrical cable and located on the package substrate. The sensor node may include that the sensor operates at a frequency band for communicating with an electronic control unit (ECU) communicatively coupled to the sensor node. The sensor node may have a filter communicatively coupled to the diplexer/combiner block, the transceiver communicatively coupled to the filter, the filter substantially removes frequencies from RF signals other than the frequency band of the sensor.