公开(公告)号：US20240105599A1

公开(公告)日：2024-03-28

申请号：US17955511

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Vishal TIWARI ,  Tahir GHANI ,  Mohit K. HARAN ,  Desalegne B. TEWELDEBRHAN

IPC: H01L23/528 ,  H01L29/423

CPC classification number: H01L23/528 ,  H01L29/4232

Abstract: Mushroomed via structures for trench contact or gate contact are described. In an example, an integrated circuit structure includes a trench contact structure over an epitaxial source or drain structure. A dielectric layer is over the trench contact structure. A trench contact via is in an opening in the dielectric layer, the trench contact via in contact with the trench contact structure. A trench contact via extension is on the trench contact via. The trench contact via extension above the dielectric layer and extending laterally beyond the trench contact via.

公开(公告)号：US20240030348A1

公开(公告)日：2024-01-25

申请号：US18374959

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Leonard P. GULER ,  Dax M. CRUM ,  Tahir GHANI

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7856 ,  H01L21/02603 ,  H01L21/823481 ,  H01L23/5226 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/42392 ,  H01L2029/7858

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

公开(公告)号：US20240030067A1

公开(公告)日：2024-01-25

申请号：US18374976

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Tahir GHANI ,  Nadia M. RAHHAL-ORABI ,  Subhash M. JOSHI ,  Joseph M. STEIGERWALD ,  Jason W. KLAUS ,  Jack HWANG ,  Ryan MACKIEWICZ

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L21/285 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L29/785 ,  H01L21/76831 ,  H01L21/76849 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66477 ,  H01L29/517 ,  H01L29/78 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/518 ,  H01L29/665 ,  H01L29/16 ,  H01L29/456 ,  H01L21/28123 ,  H01L21/28562 ,  H01L23/535 ,  H01L2029/7858 ,  H01L29/495 ,  H01L2924/0002

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20230420545A1

公开(公告)日：2023-12-28

申请号：US18367292

申请日：2023-09-12

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Byron HO ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

公开(公告)号：US20230387324A1

公开(公告)日：2023-11-30

申请号：US18228139

申请日：2023-07-31

Applicant: Intel Corporation

Inventor： Glenn GLASS ,  Anand MURTHY ,  Biswajeet GUHA ,  Tahir GHANI ,  Susmita GHOSE ,  Zachary GEIGER

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392

Abstract: Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.

公开(公告)号：US20230290851A1

公开(公告)日：2023-09-14

申请号：US17693156

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  YenTing CHIU ,  Tahir GHANI

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having additive gate structures are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric, and an intervening conductive seed layer between the P-type conductive layer and the first gate dielectric. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric, and the intervening conductive seed layer between the N-type conductive layer and the second gate dielectric. The P-type gate stack is in contact with the N-type gate stack.

公开(公告)号：US20230290778A1

公开(公告)日：2023-09-14

申请号：US17694266

申请日：2022-03-14

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  YenTing CHIU ,  Tahir GHANI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/775 ,  H01L29/78391 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6684 ,  H01L29/66742

Abstract: Gate-all-around integrated circuit structures having dual metal gates and gate dielectrics with a single polarity dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric including a high-k dielectric layer and a dipole material layer. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having a mid-gap conductive layer over a second gate dielectric including the high-k dielectric layer and the dipole material layer.

公开(公告)号：US20230215934A1

公开(公告)日：2023-07-06

申请号：US18120920

申请日：2023-03-13

Applicant: Intel Corporation

Inventor： Szuya S. LIAO ,  Michael L. HATTENDORF ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/6656 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/165

Abstract: Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure. The semiconductor structure also includes one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins.

公开(公告)号：US20230207700A1

公开(公告)日：2023-06-29

申请号：US18113576

申请日：2023-02-23

Applicant: Intel Corporation

Inventor： Mauro J. KOBRINSKY ,  Stephanie BOJARSKI ,  Babita DHAYAL ,  Biswajeet GUHA ,  Tahir GHANI

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/78618 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L21/823814 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/823807 ,  H01L29/78651 ,  H01L2029/7858

Abstract: Integrated circuit structures having partitioned source or drain contact structures, and methods of fabricating integrated circuit structures having partitioned source or drain contact structures, are described. For example, an integrated circuit structure includes a fin. A gate stack is over the fin. A first epitaxial source or drain structure is at a first end of the fin. A second epitaxial source or drain structure is at a second end of the fin. A conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures. The conductive contact structure has a first portion partitioned from a second portion.

公开(公告)号：US20230207623A1

公开(公告)日：2023-06-29

申请号：US17561715

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mohammad HASAN ,  Mohit K. HARAN ,  Mauro J. KOBRINSKY ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/6675 ,  H01L29/78672

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a vertical stack of semiconductor channels, a source on a first side of the vertical stack of semiconductor channels, and a drain on a second side of the vertical stack of semiconductor channels, In an embodiment, a metal is below the source and in direct contact with the source, where a centerline of the metal is substantially aligned with a centerline of the source.