公开(公告)号：US12113117B2

公开(公告)日：2024-10-08

申请号：US18130326

申请日：2023-04-03

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-ching Lin ,  Raseong Kim ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Ian Young

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H03H9/17

CPC classification number: H01L29/516 ,  H01L27/0886 ,  H01L29/42356 ,  H01L29/78391 ,  H01L29/7851 ,  H03H9/17

Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.

公开(公告)号：US12100731B2

公开(公告)日：2024-09-24

申请号：US16914161

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  I-Cheng Tung ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Matthew Metz ,  Uygar Avci

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L28/65 ,  H01L27/0629 ,  H01L28/55

Abstract: A capacitor device, such as a metal insulator metal (MIM) capacitor includes a seed layer including tantalum, a first electrode on the seed layer, where the first electrode includes at least one of ruthenium or iridium and an insulator layer on the seed layer, where the insulator layer includes oxygen and one or more of Sr, Ba or Ti. In an exemplary embodiment, the insulator layer is a crystallized layer having a substantially smooth surface. A crystallized insulator layer having a substantially smooth surface facilitates low electrical leakage in the MIM capacitor. The capacitor device further includes a second electrode layer on the insulator layer, where the second electrode layer includes a second metal or a second metal alloy.

公开(公告)号：US12048165B2

公开(公告)日：2024-07-23

申请号：US16914140

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Sou-Chi Chang ,  Shriram Shivaraman ,  I-Cheng Tung ,  Tobias Brown-Heft ,  Devin R. Merrill ,  Che-Yun Lin ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Matthew V. Metz

IPC: H10B53/00 ,  G11C11/22 ,  H01G4/008 ,  H01L27/08 ,  H01L49/02 ,  H10B53/10

CPC classification number: H10B53/00 ,  G11C11/221 ,  H01G4/008 ,  H01L27/0805 ,  H01L28/65 ,  H10B53/10

Abstract: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

公开(公告)号：US20240114695A1

公开(公告)日：2024-04-04

申请号：US17957560

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Nazila Haratipour ,  Christopher Neumann ,  Shriram Shivaraman ,  Brian Doyle ,  Sarah Atanasov ,  Bernal Granados Alpizar ,  Uygar Avci

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: Apparatuses, memory systems, capacitor structures, and techniques related to anti-ferroelectric capacitors having a cerium oxide doped hafnium zirconium oxide based anti-ferroelectric are described. A capacitor includes layers of hafnium oxide, cerium oxide, and zirconium oxide between metal electrodes. The cerium of the cerium oxide provides a mid gap state to protect the hafnium zirconium oxide during operation.

公开(公告)号：US20240112731A1

公开(公告)日：2024-04-04

申请号：US17957957

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Saima Siddiqui ,  Sarah Atanasov ,  Bernal Granados Alpizar ,  Uygar Avci

IPC: G11C13/00 ,  G11C11/22 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C11/22 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Techniques and mechanisms for operating a ferroelectric (FE) circuit element as a cell of a crossbar memory array. In an embodiment, the crossbar memory array comprises a bit line, a word line, and a data storage cell which includes a circuit element that extends to each of the bit line and the word line. The data storage cell is a FE circuit element which comprises terminals, each at a different respective one of the bit line or the word line, and one or more material layers between said terminals. One such layer comprises a FE nitride or a FE oxide. The FE circuit element is operable to selectively enable, or disable, operation as a diode. In another embodiment, the memory array is coupled to circuitry which corresponds a given mode of operation of the FE circuit element to a particular data bit value.

公开(公告)号：US11695051B2

公开(公告)日：2023-07-04

申请号：US16369517

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Ashish Penumatcha ,  Seung Hoon Sung ,  Scott Clendenning ,  Uygar Avci ,  Ian A. Young ,  Jack T. Kavalieros

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a FinFET transistor on the substrate. The FinFET transistor includes a fin structure having a channel area, a source area, and a drain area. The FinFET transistor further includes a gate dielectric area between spacers above the channel area of the fin structure and below a top surface of the spacers; spacers above the fin structure and around the gate dielectric area; and a metal gate conformally covering and in direct contact with sidewalls of the spacers. The gate dielectric area has a curved surface. The metal gate is in direct contact with the curved surface of the gate dielectric area. Other embodiments may be described and/or claimed.

公开(公告)号：US20230200080A1

公开(公告)日：2023-06-22

申请号：US17558419

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Uygar Avci

IPC: H01L27/11514 ,  G11C11/22 ,  H01L27/11504

CPC classification number: H01L27/11514 ,  G11C11/221 ,  H01L27/11504

Abstract: Three-dimensional ferroelectric memory cell architectures are discussed related to improved memory cell performance and density. Such three-dimensional ferroelectric memory cell architectures include groups of vertically stacked transistors accessed by vertical bit lines and horizontal word lines. Groups of such stacks of transistors are arrayed laterally. Adjacent transistor stacks are separated by isolation material or memory structures inclusive of capacitor structures or plate line structures.

公开(公告)号：US20230197860A1

公开(公告)日：2023-06-22

申请号：US17560069

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Carl H. Naylor ,  Kirby Maxey ,  Chelsey Dorow ,  Sudarat Lee ,  Kevin O'Brien ,  Ashish V. Penumatcha ,  Scott B. Clendenning ,  Uygar Avci ,  Matthew Metz

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/66969 ,  H01L29/4908

Abstract: A metal chalcogenide material layer of lower quality provides a transition between a metal chalcogenide material layer of higher quality and a gate insulator material that separates the metal chalcogenide material layers from a gate electrode of a metal-oxide semiconductor field effect transistor (MOSFET) structure. Gate insulator material may be more readily initiated and/or or precisely controlled to a particular thickness when formed on lower quality metal chalcogenide material. Accordingly, such a material stack may be integrated into a variety of transistor structures, including multi-gate, multi-channel nanowire or nanosheet transistor structures.

公开(公告)号：US20230197135A1

公开(公告)日：2023-06-22

申请号：US17558440

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek Anil Sharma ,  Uygar Avci

IPC: G11C11/22 ,  H01L23/48 ,  H01L27/11507 ,  H01L27/11509 ,  H01L23/528

CPC classification number: G11C11/2297 ,  G11C11/221 ,  H01L23/481 ,  H01L23/5286 ,  H01L27/11507 ,  H01L27/11509

Abstract: Integrated circuits with embedded memory that includes ferroelectric capacitors having first conductor structures coupled to an underlying array of access transistors, and second conductors coupled to independent plate lines that are shunted by a metal strap having a pitch similar to that of the capacitors. The independent plate lines may reduce bit-cell disturbs and/or simplify read/write process while the plate line straps reduce series resistance of the plate lines. The metal straps may be subtractively patterned lines in direct contact with the second capacitor conductors, or may be damascene structures coupled to the second capacitor conductors through vias that also have a pitch similar to that of the capacitors.

公开(公告)号：US11646374B2

公开(公告)日：2023-05-09

申请号：US16232615

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Ashish Verma Penumatcha ,  Tanay Gosavi ,  Uygar Avci ,  Ian A. Young

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  G11C11/22 ,  H01L29/417 ,  H01L21/28

CPC classification number: H01L29/78391 ,  G11C11/223 ,  G11C11/2275 ,  H01L29/40111 ,  H01L29/41725 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684

Abstract: Embodiments herein describe techniques for a semiconductor device including a gate stack with a ferroelectric-oxide layer above a channel layer and in contact with the channel layer, and a top electrode above the ferroelectric-oxide layer. The ferroelectric-oxide layer includes a domain wall between an area under a nucleation point of the top electrode and above a separation line of the channel layer between an ON state portion and an OFF state portion of the channel layer. A resistance between a source electrode and a drain electrode is modulated in a range between a first resistance value and a second resistance value, dependent on a position of the domain wall within the ferroelectric-oxide layer, a position of the ON state portion of the channel layer, and a position of the OFF state portion of the channel layer. Other embodiments may be described and/or claimed.