公开(公告)号：US09882006B2

公开(公告)日：2018-01-30

申请号：US15340624

申请日：2016-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  Nicolas Loubet ,  Junli Wang

IPC: H01L29/10 ,  H01L29/161 ,  H01L29/66 ,  H01L21/225 ,  H01L21/311 ,  H01L21/02 ,  H01L29/78 ,  H01L29/167

CPC classification number: H01L29/785 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/2256 ,  H01L21/31116 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66818

Abstract: A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense out Ge and diffuse the Ge into the region of the underlying fin to form a channel region with Ge in the fin.

公开(公告)号：US09837440B2

公开(公告)日：2017-12-05

申请号：US14174914

申请日：2014-02-07

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Alexander Reznicek ,  Soon-Cheon Seo

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L27/1211 ,  H01L21/823412 ,  H01L29/04 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers.

公开(公告)号：US09805991B2

公开(公告)日：2017-10-31

申请号：US14830969

申请日：2015-08-20

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L29/66 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L27/088 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L21/845 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76213 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

公开(公告)号：US09768272B2

公开(公告)日：2017-09-19

申请号：US14870936

申请日：2015-09-30

Applicant: International Business Machines Corporation

Inventor： Pouya Hashemi ,  Hong He ,  Alexander Reznicek ,  Tenko Yamashita

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/6656 ,  H01L21/30604 ,  H01L21/3081 ,  H01L29/0642 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A replacement gate FinFET manufacturing process in which the source/drain regions, gate structure and gate spacer are all defined by utilizing a single sidewall image transfer technique is provided. In the present application, the source/drain region (i.e., area) are defined by a mandrel structure, while the area for the functional gate structure are defined by the distance between spacers that are located on a pair of neighboring mandrel structures. The gate spacer is defined by the spacer present on the mandrel structures. In some embodiments, semiconductor fin erosion due to gate and gate spacer formation can be reduced or even eliminated.

公开(公告)号：US09728534B2

公开(公告)日：2017-08-08

申请号：US14877186

申请日：2015-10-07

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L27/088 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/3085 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.

公开(公告)号：US20170194435A1

公开(公告)日：2017-07-06

申请号：US15467821

申请日：2017-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Hong He ,  Juntao Li

IPC: H01L29/10 ,  H01L29/04 ,  H01L29/78 ,  H01L21/28 ,  H01L29/161

Abstract: A semiconductor structure includes a material stack located on a surface of a semiconductor substrate. The material stack includes, from bottom to top, a silicon germanium alloy portion that is substantially relaxed and defect-free and a semiconductor material pillar that is defect-free. A dielectric material structure surrounds sidewalls of the material stack and is present on exposed portions of the semiconductor substrate.

公开(公告)号：US20170194250A1

公开(公告)日：2017-07-06

申请号：US15251490

申请日：2016-08-30

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L23/525

CPC classification number: H01L23/5252

Abstract: A method for manufacturing a semiconductor device includes forming a fin extending between first and second pads on a substrate, removing a central portion of the fin to create an opening between a first part of the fin extending from the first pad and a second part of the fin extending from the second pad, growing first and second epitaxial layers in the opening on a side of respective first and second parts of the fin, stopping the growth of the first and second epitaxial layers prior to merging, forming a silicide layer on the first and second pads, first and second parts of the fin and first and second epitaxial layers, wherein there is a gap between portions of the silicide layer on the first and second epitaxial layers in the opening, and depositing a dielectric layer on the silicide layer, filling in the gap.

公开(公告)号：US09666527B1

公开(公告)日：2017-05-30

申请号：US14969717

申请日：2015-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L23/52 ,  H01L23/525 ,  H01L29/06 ,  H01L21/764 ,  H01L21/768 ,  H01L27/02

CPC classification number: H01L23/5256 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/53209 ,  H01L27/0207 ,  H01L29/0649

Abstract: A fuse includes a semiconductor layer having a dielectric material formed thereon. An epitaxially grown material is formed in a trench within the dielectric material. The epitaxially grown material includes a peak region. A fuse metal is formed over the peak region and extends along sidewalls of the trench and over the dielectric material outside the trench. Contacts are formed outside the trench connecting to fuse metal over the dielectric material.

公开(公告)号：US09647092B2

公开(公告)日：2017-05-09

申请号：US14984445

申请日：2015-12-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Juntao Li ,  Chih-Chao Yang ,  Yunpeng Yin

IPC: H01L23/525 ,  H01L23/62 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/768 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/76897 ,  H01L21/845 ,  H01L23/5256 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/785

Abstract: An e-Fuse structure is provided on a surface of an insulator layer of a semiconductor-on-insulator substrate (SOI). The e-Fuse structure includes a first metal semiconductor alloy structure of a first thickness, a second metal semiconductor alloy structure of the first thickness, and a metal semiconductor alloy fuse link is located laterally between and connected to the first and second metal semiconductor alloy structures. The metal semiconductor alloy fuse link has a second thickness that is less than the first thickness.

公开(公告)号：US09634117B2

公开(公告)日：2017-04-25

申请号：US15075260

申请日：2016-03-21

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/283 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L21/768 ,  H01L29/165

CPC classification number: H01L23/535 ,  H01L21/283 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity.