公开(公告)号：US09601576B2

公开(公告)日：2017-03-21

申请号：US14256225

申请日：2014-04-18

Applicant: International Business Machines Corporation

Inventor： Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/00 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L29/06 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: Fin stacks including a silicon germanium alloy portion and a silicon portion are formed on a surface of a substrate. Sacrificial gate structures are then formed straddling each fin stack. Silicon germanium alloy portions that are exposed are oxidized, while silicon germanium alloy portions that are covered by the sacrificial gate structures are not oxidized. A dielectric material having a topmost surface that is coplanar with a topmost surface of each sacrificial gate structure is formed, and thereafter each sacrificial gate structure is removed. Non-oxidized silicon germanium alloy portions are removed suspending silicon portions that were present on each non-oxidized silicon germanium alloy portion. A functional gate structure is then formed around each suspended silicon portion. The oxidized silicon germanium alloy portions remain and provide stress to a channel portion of the suspended silicon portions.

公开(公告)号：US20170069715A1

公开(公告)日：2017-03-09

申请号：US15354142

申请日：2016-11-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Isaac Lauer ,  Tenko Yamashita ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L23/562 ,  B82Y10/00 ,  H01L21/02403 ,  H01L21/02603 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

Abstract: A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

Abstract translation: 纳米线装置包括形成在基板上的第一部件和与基板上的第一部件分开设置的第二部件。 纳米线被配置为将第一部件连接到第二部件。 沿着纳米线的跨度形成锚垫，并且构造成沿着跨度支撑纳米线以防止下垂。

公开(公告)号：US09558930B2

公开(公告)日：2017-01-31

申请号：US14458887

申请日：2014-08-13

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Szu-Lin Cheng ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/324 ,  H01L23/528

CPC classification number: H01L23/53228 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/02351 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a method of forming a wiring layer on a wafer is provided which includes: depositing a HSQ layer onto the wafer; cross-linking a first portion(s) of the HSQ layer using e-beam lithography; depositing a hardmask material onto the HSQ layer; patterning the hardmask using optical lithography, wherein the patterned hardmask covers a second portion(s) of the HSQ layer; patterning the HSQ layer using the patterned hardmask in a manner such that i) the first portion(s) of the HSQ layer remain and ii) the second portion(s) of the HSQ layer covered by the patterned hardmask remain, wherein by way of the patterning step trenches are formed in the HSQ layer; and filling the trenches with a conductive material to form the wiring layer on the wafer.

Abstract translation: 一方面，提供了一种在晶片上形成布线层的方法，包括：将HSQ层沉积到晶片上; 使用电子束光刻术交联HSQ层的第一部分; 将硬掩模材料沉积到HSQ层上; 使用光学平版印刷图案化硬掩模，其中图案化的硬掩模覆盖HSQ层的第二部分; 使用图案化的硬掩模以使得i）HSQ层的第一部分保留并且ii）被图案化硬掩模覆盖的HSQ层的第二部分保留的方式图案化HSQ层，其中通过 图案化步骤沟槽形成在HSQ层中; 并用导电材料填充沟槽以在晶片上形成布线层。

公开(公告)号：US09543388B2

公开(公告)日：2017-01-10

申请号：US15076880

申请日：2016-03-22

Applicant: International Business Machines Corporation

Inventor： Gen P. Lauer ,  Isaac Lauer ,  Alexander Reznicek ,  Jeffrey W. Sleight

IPC: H01L21/00 ,  H01L29/10 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/324 ,  H01L21/3065 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/78 ,  G05B19/19 ,  H01L21/02

CPC classification number: H01L29/1054 ,  G05B19/19 ,  G05B2219/45032 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/7849 ,  H01L29/785

Abstract: A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.

Abstract translation: 访问具有nFET和pFET区域的硅锗绝缘体（SGOI）晶片，SGOI晶片具有具有第一锗（Ge）浓度的硅锗（SiGe）层，以及nFET和pFET上的第一氧化物层，并且去除第一 pFET上的氧化层。 然后，将pFET中的SiGe层中的第一Ge浓度提高到第二Ge浓度，并且去除nFET上的第一氧化物层。 然后，使nFET中的第一Ge浓度的SiGe层凹陷，使得SiGe层与第二Ge浓度的pFET中的SiGe层成平面。 然后，在nFET中的SGOI上生长硅（Si）层，并且在pFET中生长第三浓度的SiGe层，其中第三浓度的SiGe层与生长的nFET Si层成平面。

公开(公告)号：US20170005188A1

公开(公告)日：2017-01-05

申请号：US14948509

申请日：2015-11-23

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer

IPC: H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.

Abstract translation: 半导体器件包括第一源极/漏极区域，第二源极/漏极区域和插入在第一和第二源极/漏极区域之间的栅极区域。 至少一个纳米线具有锚定到第一源极/漏极区域的第一端和锚定到第二源极/漏极区域的相对的第二端，使得纳米线悬浮在栅极区域中的晶片上方。 至少一个栅极电极位于栅极区域中。 栅电极接触纳米线的整个表面以限定栅极全部配置。 至少一对氧化间隔物围绕至少一个栅电极，以将至少一个栅电极与第一和第二源极/漏极区电隔离。

公开(公告)号：US20160379820A1

公开(公告)日：2016-12-29

申请号：US14948541

申请日：2015-11-23

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Isaac Lauer ,  Kuen-Ting Shiu ,  Jeng-Bang Yau

IPC: H01L21/02 ,  H01L21/306

CPC classification number: H01L21/02455 ,  H01L21/02538 ,  H01L21/02614 ,  H01L21/30604 ,  H01L29/0642 ,  H01L29/20 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further includes at least one semiconductor fin on the III-V buffer layer. The semiconductor fin includes a III-V channel portion. Either the wafer or the semiconductor fin includes an oxidized III-V portion interposed between the III-V channel portion and the III-V buffer layer to prevent current leakage to the bulk layer.

公开(公告)号：US09496184B2

公开(公告)日：2016-11-15

申请号：US14245627

申请日：2014-04-04

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/8238 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/24 ,  H01L29/10 ,  H01L29/45 ,  H01L29/735 ,  H01L27/06 ,  H01L21/84

CPC classification number: H01L21/8249 ,  H01L21/244 ,  H01L21/84 ,  H01L27/0623 ,  H01L29/1008 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66545 ,  H01L29/735

Abstract: In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.

Abstract translation: 一方面，在晶片上制造双极晶体管器件的方法包括以下步骤。 在晶片上形成虚拟栅极，其中伪栅极存在于作为双极晶体管的基极的晶片的一部分上。 晶圆被掺杂以在虚拟栅极的两侧上形成发射极和集电极区域。 介电填料层沉积在围绕虚拟栅极的晶片上。 对绝缘填料层选择性地去除伪栅极，从而露出基底。 基座凹进。 碱从由SiGe，Ge和III-V材料组成的组中选择的外延材料再生长。 触点形成在基座上。 还提供了用于共同制造双极晶体管和CMOS FET器件的技术。

公开(公告)号：US20160284805A1

公开(公告)日：2016-09-29

申请号：US15181680

申请日：2016-06-14

Applicant: International Business Machines Corporation

Inventor： Guy M. Cohen ,  Isaac Lauer ,  Alexander Reznicek ,  Jeffrey W. Sleight

IPC: H01L29/41 ,  H01L29/06 ,  H01L29/417 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L29/413 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41758 ,  H01L29/4966 ,  H01L29/775

Abstract: A device that includes: a substrate layer; a first set of source/drain component(s) defining an nFET (n-type field-effect transistor) region; a second set of source/drain component(s) defining a pFET (p-type field-effect transistor) region; a first suspended nanowire, at least partially suspended over the substrate layer in the nFET region and made from III-V material; and a second suspended nanowire, at least partially suspended over the substrate layer in the pFET region and made from Germanium-containing material. In some embodiments, the first suspended nanowire and the second suspended nanowire are fabricated by adding appropriate nanowire layers on top of a Germanium-containing release layer, and then removing the Germanium-containing release layers so that the nanowires are suspended.

Abstract translation: 一种装置，包括：基底层; 限定nFET（n型场效应晶体管）区域的第一组源/漏分量; 限定pFET（p型场效应晶体管）区域的第二组源/漏分量; 至少部分地悬浮在nFET区域中的衬底层上并由III-V材料制成的第一悬浮的纳米线; 和第二悬浮的纳米线，其至少部分地悬浮在pFET区域中的衬底层上并由含锗材料制成。 在一些实施方案中，通过在含锗释放层的顶部上加入适当的纳米线层，然后除去含锗释放层以使纳米线悬浮，制造第一悬浮的纳米线和第二悬浮的纳米线。

公开(公告)号：US09437613B2

公开(公告)日：2016-09-06

申请号：US15057900

申请日：2016-03-01

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L27/085 ,  H01L27/092 ,  H01L29/66 ,  H01L29/778 ,  H01L21/335 ,  H01L27/12 ,  H01L29/06 ,  H01L29/205 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/1203 ,  H01L21/823412 ,  H01L21/8252 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1029 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41783 ,  H01L29/78696

Abstract: In one aspect, a method of forming a multiple VT device structure includes the steps of: forming an alternating series of channel and barrier layers as a stack having at least one first channel layer, at least one first barrier layer, and at least one second channel layer; defining at least one first and at least one second active area in the stack; selectively removing the at least one first channel/barrier layers from the at least one second active area, such that the at least one first channel layer and the at least one second channel layer are the top-most layers in the stack in the at least one first and the at least one second active areas, respectively, wherein the at least one first barrier layer is configured to confine charge carriers to the at least one first channel layer in the first active area.

Abstract translation: 一方面，一种形成多个VT器件结构的方法包括以下步骤：形成交替的沟道和阻挡层系列作为具有至少一个第一沟道层，至少一个第一势垒层和至少一个第二栅极层 通道层; 限定所述堆叠中的至少一个第一和至少一个第二有效区域; 选择性地从所述至少一个第二有源区域去除所述至少一个第一沟道/势垒层，使得所述至少一个第一沟道层和所述至少一个第二沟道层至少在所述堆叠中的最顶层 一个第一和至少一个第二有源区，其中至少一个第一势垒层被配置为将电荷载流子限制在第一有源区中的至少一个第一沟道层。

公开(公告)号：US09431301B1

公开(公告)日：2016-08-30

申请号：US14964968

申请日：2015-12-10

Applicant: International Business Machines Corporation

Inventor： Jack O. Chu ,  Szu Lin Cheng ,  Isaac Lauer ,  Kuen-Ting Shiu ,  Jeng-Bang Yau

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10 ,  H01L29/205 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/762 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785

Abstract: A semiconductor structure includes a plurality of semiconductor fins located on a semiconductor substrate, in which each of the semiconductor fins comprises a sequential stack of a buffered layer including a III-V semiconductor material and a channel layer including a III-V semiconductor material. The semiconductor structure further includes a gap filler material surrounding the semiconductor fins and including a plurality of trenches therein. The released portions of the channel layers of the semiconductor fins located in the trenches constitute nanowire channels of the semiconductor structure, and opposing end portions of the channel layers of the semiconductor fins located outside of the trenches constitute a source region and a drain region of the semiconductor structure, respectively. In addition, the semiconductor structure further includes a plurality of gates structures located within the trenches that surround the nanowire channels in a gate all around configuration.

Abstract translation: 半导体结构包括位于半导体衬底上的多个半导体鳍片，其中每个半导体鳍片包括包括III-V半导体材料的缓冲层和包括III-V半导体材料的沟道层的顺序堆叠。 半导体结构还包括围绕半导体鳍片并且在其中包括多个沟槽的间隙填充材料。 位于沟槽中的半导体鳍片的沟道层的释放部分构成半导体结构的纳米线通道，并且位于沟槽外侧的半导体鳍片的沟道层的相对端部构成源极区域和漏极区域 半导体结构。 此外，半导体结构还包括位于沟槽内的多个门结构，其围绕纳米线通道围绕配置的栅极。