公开(公告)号：US20050170582A1

公开(公告)日：2005-08-04

申请号：US11068848

申请日：2005-03-02

申请人： Takeo Furuhata ,  Ichiro Mizushima ,  Akiko Sekihara ,  Motoya Kishida ,  Tsubasa Harada ,  Takashi Nakao

发明人： Takeo Furuhata ,  Ichiro Mizushima ,  Akiko Sekihara ,  Motoya Kishida ,  Tsubasa Harada ,  Takashi Nakao

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L31/119

CPC分类号： H01L21/76847 ,  H01L21/76864 ,  H01L27/10867 ,  H01L29/945

摘要： A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.

公开(公告)号：US20050167720A1

公开(公告)日：2005-08-04

申请号：US11068853

申请日：2005-03-02

申请人： Takeo Furuhata ,  Ichiro Mizushima ,  Akiko Sekihara ,  Motoya Kishida ,  Tsubasa Harada ,  Takashi Nakao

发明人： Takeo Furuhata ,  Ichiro Mizushima ,  Akiko Sekihara ,  Motoya Kishida ,  Tsubasa Harada ,  Takashi Nakao

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L31/119

CPC分类号： H01L21/76847 ,  H01L21/76864 ,  H01L27/10867 ,  H01L29/945

摘要： A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.

公开(公告)号：US06906384B2

公开(公告)日：2005-06-14

申请号：US10096655

申请日：2002-03-14

申请人： Takashi Yamada ,  Tsutomu Sato ,  Shinichi Nitta ,  Hajime Nagano ,  Ichiro Mizushima ,  Hisato Oyamatsu ,  Yoshihiro Minami ,  Shinji Miyano ,  Osamu Fujii

发明人： Takashi Yamada ,  Tsutomu Sato ,  Shinichi Nitta ,  Hajime Nagano ,  Ichiro Mizushima ,  Hisato Oyamatsu ,  Yoshihiro Minami ,  Shinji Miyano ,  Osamu Fujii

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L27/10861 ,  H01L21/76243 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/78639

摘要： A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

摘要翻译： 半导体器件包括第一和第二半导体层以及第一和第二MOS晶体管。 第一半导体层设置在半导体衬底上并与之电连接。 第二半导体层设置在第一半导体层附近，并且经由绝缘膜和空腔中的一个形成在半导体基板的上方。 第一和第二MOS晶体管分别设置在第一和第二半导体层上，并且各自具有平行于第一和第二半导体层之间的边界排列的栅电极。

公开(公告)号：US06846750B1

公开(公告)日：2005-01-25

申请号：US09604724

申请日：2000-06-28

申请人： Tokuhisa Ohiwa ,  Shoji Seta ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Akihiro Kojima ,  Junko Ohuchi ,  Tsukasa Azuma ,  Hideo Ichinose ,  Ichiro Mizushima

发明人： Tokuhisa Ohiwa ,  Shoji Seta ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Akihiro Kojima ,  Junko Ohuchi ,  Tsukasa Azuma ,  Hideo Ichinose ,  Ichiro Mizushima

IPC分类号： H01L21/302 ,  H01L21/033 ,  H01L21/30 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L21/461

CPC分类号： H01L21/76802 ,  H01L21/0331 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/76816 ,  H01L21/7682

摘要： According to the present invention, there is provided a method of manufacturing a semiconductor device, where a soluble thin film which is soluble in a dissolving liquid is used. According to the method of the present invention, when a soluble thin film is formed between a film to be processed which should be patterned and a mask pattern, it becomes possible to remove the mask pattern by lifting-off. On the other hand, when the thin film is used for a dummy layer for forming an air wiring structure, the dummy layer can be removed without performing ashing using oxygen plasma.

摘要翻译： 根据本发明，提供一种制造半导体器件的方法，其中使用可溶于溶解液的可溶性薄膜。 根据本发明的方法，当在要被图案化的被处理膜和掩模图案之间形成可溶性薄膜时，可以通过剥离来去除掩模图案。 另一方面，当薄膜用于形成空气布线结构的虚拟层时，可以去除虚拟层而不用氧等离子体进行灰化。

公开(公告)号：US06617226B1

公开(公告)日：2003-09-09

申请号：US09609107

申请日：2000-06-30

申请人： Kyoioni Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoioni Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L2120

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

摘要翻译： 在使用外延生长方法选择性地在硅衬底上生长其上要形成元素的外延层时，形成外延层，以便在作为元件隔离绝缘膜的热氧化膜上方向上延伸， 以防止形成小平面。 随后，通过CMP去除外延层的不需要的部分以完成STI元件隔离结构。

公开(公告)号：US06342421B1

公开(公告)日：2002-01-29

申请号：US09098736

申请日：1998-06-18

申请人： Yuichiro Mitani ,  Ichiro Mizushima ,  Shigeru Kambayashi ,  Hirotaka Nishino ,  Masahiro Kashiwagi

发明人： Yuichiro Mitani ,  Ichiro Mizushima ,  Shigeru Kambayashi ,  Hirotaka Nishino ,  Masahiro Kashiwagi

IPC分类号： H01L27108

CPC分类号： H01L29/0847 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/41725 ,  H01L29/41733 ,  H01L29/456 ,  H01L29/458 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78618

摘要： A method of manufacturing a semiconductor device including the steps of forming an insulating film on a silicon region of a substrate having the silicon region on a surface the insulating film having an opening for forming an exposed region of the silicon region, supplying a gas containing a halogen onto the silicon region, and supplying a source gas of silicon onto the silicon region, thereby selectively depositing the silicon on the exposed region of the silicon region.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在具有用于形成硅区域的暴露区域的开口的绝缘膜的表面上具有硅区域的衬底的硅区上形成绝缘膜的步骤，提供含有 卤素到硅区域，并且将硅源气体供应到硅区域上，由此在硅区域的暴露区域上选择性地沉积硅。

公开(公告)号：US08673786B2

公开(公告)日：2014-03-18

申请号：US13424811

申请日：2012-03-20

申请人： Kei Watanabe ,  Ichiro Mizushima

发明人： Kei Watanabe ,  Ichiro Mizushima

IPC分类号： H01L21/311

CPC分类号： B81C1/00492 ,  B81C2201/0149 ,  B81C2201/0198 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

摘要： According to one embodiment, a method for manufacturing a microstructure includes forming a guide film on a patterning material, forming a cured film, forming a mask member, and performing processing of the patterning material using the mask member as a mask. An opening is made in the guide film. An upper surface of the guide film is hydrophilic, a side surface of the opening is hydrophobic. The forming the cured film includes applying a solution to cover the patterning material and the guide film, separating the solution into a hydrophobic block and a hydrophilic block, and curing the solution. The solution contains an amphiphilic polymer having a hydrophobic portion and a hydrophilic portion. A length of the hydrophobic portion is longer than a length of the hydrophilic portion. The mask member is formed by removing the hydrophilic block from the cured film.

摘要翻译： 根据一个实施例，微结构的制造方法包括在图案形成材料上形成引导膜，形成固化膜，形成掩模部件，并使用掩模部件作为掩模进行图案形成材料的处理。 在引导膜中形成一个开口。 引导膜的上表面是亲水性的，开口的侧表面是疏水性的。 形成固化膜包括施加溶液以覆盖图案形成材料和引导膜，将溶液分离成疏水性嵌段和亲水性嵌段，并固化该溶液。 该溶液含有具有疏水部分和亲水部分的两亲性聚合物。 疏水部分的长度长于亲水部分的长度。 通过从固化膜除去亲水性嵌段形成掩模构件。

公开(公告)号：US07989856B2

公开(公告)日：2011-08-02

申请号：US12335701

申请日：2008-12-16

申请人： Masakazu Goto ,  Nobutoshi Aoki ,  Takashi Izumida ,  Kimitoshi Okano ,  Satoshi Inaba ,  Ichiro Mizushima

发明人： Masakazu Goto ,  Nobutoshi Aoki ,  Takashi Izumida ,  Kimitoshi Okano ,  Satoshi Inaba ,  Ichiro Mizushima

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/7845

摘要： A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode.

摘要翻译： 翅片晶体管包括：衬底; 形成在所述基板上的多个半导体翅片; 覆盖半导体鳍片的沟道区域的栅电极; 以及作为用于包括在栅极电极的区域中的半导体鳍片的应力源的构件和设置在半导体鳍片之间的区域，并且该构件由与栅电极不同的材料制成。

公开(公告)号：US20110024827A1

公开(公告)日：2011-02-03

申请号：US12904231

申请日：2010-10-14

申请人： Fumitaka ARAI ,  Ichiro Mizushima ,  Makoto Mizukami

发明人： Fumitaka ARAI ,  Ichiro Mizushima ,  Makoto Mizukami

IPC分类号： H01L29/792 ,  H01L29/78

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42348 ,  H01L29/792

摘要： A nonvolatile semiconductor memory according to an aspect of the invention comprises a semiconductor substrate which has an SOI region and an epitaxial region at its surface, a buried oxide film arranged on the semiconductor substrate in the SOI region, an SOI layer arranged on the buried oxide film, a plurality of memory cells arranged on the SOI layer, an epitaxial layer arranged in the epitaxial region, and a select gate transistor arranged on the epitaxial layer, wherein the SOI layer is made of a microcrystalline layer.

摘要翻译： 根据本发明的一个方面的非易失性半导体存储器包括：在其表面具有SOI区域和外延区域的半导体衬底，设置在SOI区域中的半导体衬底上的掩埋氧化膜，布置在掩埋氧化物上的SOI层 膜，布置在SOI层上的多个存储单元，布置在外延区中的外延层和布置在外延层上的选择栅极晶体管，其中SOI层由微晶层制成。

公开(公告)号：US20110014781A1

公开(公告)日：2011-01-20

申请号：US12837025

申请日：2010-07-15

申请人： Hiroshi Itokawa ,  Ichiro Mizushima

发明人： Hiroshi Itokawa ,  Ichiro Mizushima

IPC分类号： H01L21/20

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02636 ,  H01L21/02667

摘要： According to one embodiment, a method of fabricating a semiconductor device includes forming a first insulator on a semiconductor substrate, forming a first groove on the insulator to expose at least a part of the semiconductor substrate at a bottom of the first groove, forming a first embedding film including at least germanium in the groove, melting the first embedding film by heat treatment, and crystallizing the first embedding film being melted to a single-crystalline film using the semiconductor substrate as a seed.

摘要翻译： 根据一个实施例，制造半导体器件的方法包括在半导体衬底上形成第一绝缘体，在绝缘体上形成第一凹槽，以在第一凹槽的底部露出半导体衬底的至少一部分，形成第一 将至少含有锗的包埋膜通过热处理熔化，并且使用半导体基板作为种子将第一埋层膜熔化成单晶膜。