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公开(公告)号：US20230317782A1
公开(公告)日：2023-10-05
申请号：US17656890
申请日：2022-03-29
发明人： Ruilong Xie , Dechao Guo , Kisik Choi , Oleg Gluschenkov , Shogo Mochizuki
IPC分类号： H01L29/06 , H01L29/423 , H01L29/786 , H01L29/66 , H01L21/8234 , H01L23/48
CPC分类号： H01L29/0665 , H01L29/42392 , H01L29/78618 , H01L23/481 , H01L21/823412 , H01L21/823418 , H01L29/66742
摘要： A first and a second nanosheet stack, a first source drain to the first nanosheet stack, a carrier wafer bonded to an upper surface, a bottom source drain contact located on a bottom surface of the first source drain, an epitaxial region between the bottom source drain contact and the first source drain, a second source drain adjacent to the second nanosheet stack and a top source drain contact located on an upper surface of the second source drain, the bottom source drain contact and the top source drain contact on opposite sides. Forming a first and a second nanosheet stack, forming an upper top source drain contact to first source drain adjacent to the first nanosheet stack, bonding a carrier wafer to an upper surface and forming a bottom source drain contact to a lower horizontal surface of a second source drain adjacent to the second nanosheet stack.
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公开(公告)号：US11777034B2
公开(公告)日：2023-10-03
申请号：US17468001
申请日：2021-09-07
发明人： Ruilong Xie , Chen Zhang , Jingyun Zhang , Junli Wang , Pietro Montanini
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/786 , H01L29/775 , H01L29/40 , H01L27/092 , B82Y10/00
CPC分类号： H01L29/7851 , H01L27/0922 , H01L29/0649 , H01L29/0665 , H01L29/0673 , H01L29/0847 , H01L29/401 , H01L29/41791 , H01L29/4238 , H01L29/42376 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696 , B82Y10/00
摘要： A stacked transistor device is provided. The stacked transistor device includes a nanosheet transistor device on a substrate; and a fin field effect transistor device over the nanosheet transistor device to form the stacked transistor device, wherein the fin field effect transistor device is configured to have a current flow through the fin field effect transistor device perpendicular to a current flow through the nanosheet transistor device.
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公开(公告)号：US20230307495A1
公开(公告)日：2023-09-28
申请号：US17655797
申请日：2022-03-22
发明人： Sanjay C. Mehta , Shogo Mochizuki , Ruilong Xie
IPC分类号： H01L29/06 , H01L29/423 , H01L29/786 , H01L21/8234 , H01L21/762
CPC分类号： H01L29/0649 , H01L29/0665 , H01L29/42392 , H01L29/78696 , H01L29/78618 , H01L21/823412 , H01L21/823418 , H01L21/762
摘要： A first and a second nanosheet stack, a shallow trench isolation region vertically aligned between them, a continuous dielectric layer below the first and second nanosheet stack and above the shallow trench isolation region. The shallow trench isolation region is vertically aligned with a source drain between the first and the second nanosheet stack. A method including forming a first and a second nanosheet stack on a first substrate, the first and the second nanosheet stack each including a lower nanosheet stack vertically aligned above an upper nanosheet stack, the upper nanosheet stack and the lower nanosheet stack each including alternating layers of a sacrificial material and a semiconductor channel material vertically aligned and stacked one on top of another, flipping the first substrate over, bonding an upper surface of the first substrate to an upper surface of a second substrate which includes a shallow trench isolation region.
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公开(公告)号：US20230297340A1
公开(公告)日：2023-09-21
申请号：US17700466
申请日：2022-03-21
发明人： Julien Frougier , Ruilong Xie , Kangguo Cheng , CHANRO PARK
CPC分类号： G06F7/588 , G06N10/40 , G06F9/3877
摘要： A system includes an emitter unit that generates random numbers encoded in light polarization, and a detector unit positioned with respect to the emitter. The detector receives the random numbers from the emitter and converts them into an electrical signal. The emitter unit can include a substrate; a bottom electrically conductive and optically reflective layer outward of the substrate; an active medium layer, outward of the bottom layer, configured to convert spin information carried by injected spin-polarized electrical carriers into light polarization information carried by light emitted from radiative recombination of the electrical carriers; a top electrically conductive and optically reflective layer outward of the active medium layer; a bottom electrically conductive contact electrically interconnected with the bottom layer; a top electrically conductive contact electrically interconnected with the top layer; and an electrically conductive carrier spin-polarizer layer located between, and electrically interconnected with, the bottom layer and the bottom contact.
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公开(公告)号：US11764265B2
公开(公告)日：2023-09-19
申请号：US17382289
申请日：2021-07-21
发明人： Kangguo Cheng , Ruilong Xie , Julien Frougier , Juntao Li
CPC分类号： H01L29/0847 , H01L29/0665 , H01L29/1608 , H01L29/6653 , H01L29/66545
摘要： A field effect transistor (FET) structure upon a substrate formed by forming a stack of nanosheets upon a semiconductor substrate, the stack including alternating layers of a compound semiconductor material and an elemental semiconductor material, forming a dummy gate structure upon the stack of nanosheets, recessing the stack of nanosheets in alignment with the dummy gate structure, recessing the compound semiconductor layers beyond the edges of the dummy gate, yielding indentations between adjacent semiconductor nanosheets. Further by filling the indentations with a bi-layer dielectric material, epitaxially growing source/drain regions adjacent to the nanosheet stack and bi-layer dielectric material, removing remaining portions of the compound semiconductor nanosheet layers, recessing the bi-layer dielectric material to expose an inner material layer, and forming gate structure layers in contact with first and second dielectric materials of the bi-layer dielectric material.
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公开(公告)号：US20230290823A1
公开(公告)日：2023-09-14
申请号：US17654607
申请日：2022-03-14
IPC分类号： H01L29/06 , H01L29/423 , H01L29/786 , H01L29/66 , H01L29/417 , H01L21/8234 , H01L21/768
CPC分类号： H01L29/0665 , H01L29/42392 , H01L29/78618 , H01L29/78696 , H01L29/66553 , H01L29/41733 , H01L21/823412 , H01L21/76843
摘要： A semiconductor device including a nanodevice located on a substrate, where the nanodevice includes a plurality of nanosheets. Each of the plurality of nanosheets are spaced apart from each other by a first distance. A gate located on the substrate, where the gate surrounds each of the plurality of nanosheets. A first dielectric layer located on the substrate, where the first dielectric layer is located adjacent to a sidewall of the gate. The gate has a first thickness when measured from the sidewall of one of the plurality of nanosheets to a sidewall of the first dielectric layer, where the first thickness is larger than the first distance. An inner spacer located on the substrate, where the inner spacer is wraps around an end of each of the plurality of nanosheets. The inner spacer has a second thickness, where the second thickness is substantially equal to the first distance.
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公开(公告)号：US11742354B2
公开(公告)日：2023-08-29
申请号：US17482426
申请日：2021-09-23
IPC分类号： H01L27/092 , H01L29/06 , H01L21/8238 , H01L29/66 , H01L29/78
CPC分类号： H01L27/0924 , H01L21/823821 , H01L21/823878 , H01L29/0649 , H01L29/66795 , H01L29/7851
摘要： A semiconductor device includes first and second vertical transport field-effect transistor (VTFET) devices. Each of the first and second VTFET devices includes a bottom epitaxial layer, a plurality of channel fins formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed between the channel fins, a high-κ metal gate formed between the channel fins and the first ILD layer, a top epitaxial layer formed discretely on each of the channel fins, and a trench epitaxial layer formed continuously across the top epitaxial layer, a portion of the first ILD layer also being formed between the first and second VTFET device. The semiconductor device also includes a second ILD layer formed on the portion of the first ILD layer that is between the first and second VTFET devices, the second ILD layer separating the top epitaxial layers of the first and second VTFET devices.
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公开(公告)号：US11742350B2
公开(公告)日：2023-08-29
申请号：US17482504
申请日：2021-09-23
发明人： Andrew Gaul , Chanro Park , Julien Frougier , Ruilong Xie , Andrew M. Greene , Christopher J. Waskiewicz
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/823842 , H01L21/823878
摘要： Embodiments of the present invention are directed to fabrication methods and resulting structures that provide metal gate N/P boundary control in an integrated circuit (IC) using an active gate cut and recess processing scheme. In a non-limiting embodiment of the invention, a gate cut is formed in an N/P boundary between an n-type field effect transistor (FET) and a p-type FET. A first portion of a first work function metal is removed over a channel region of the n-type FET. The gate cut prevents etching a second portion of the first work function metal. The first portion of the first work function metal is replaced with a second work function metal. The gate cut is recessed, and a conductive region is formed on the recessed surface of the gate cut. The conductive region provides electrical continuity across the N/P boundary.
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79.发明授权公开(公告)号：US11742246B2
公开(公告)日：2023-08-29
申请号：US17502210
申请日：2021-10-15
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/78 , H01L29/66 , H01L21/762
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823487 , H01L27/088 , H01L29/6653 , H01L29/6656 , H01L29/66666 , H01L29/7827
摘要： A vertical field effect transistor structure and method for fabricating the same. The structure includes a source/drain layer in contact with at least one semiconductor fin. An edge portion of the source/drain layer includes a notched region filled with a dielectric material. A spacer layer includes a first portion in contact with the source/drain layer and a second portion in contact with the dielectric material. A gate structure contacts the spacer layer and the dielectric material. The method includes forming a source/drain layer in contact with at least one semiconductor fin. A spacer layer is formed in contact with the source/drain layer. A portion of the spacer layer is removed to expose an end portion of the source/drain layer. The exposed end portion of the source/drain layer is recessed to form a notched region within the source/drain layer. A dielectric layer is formed within the notched region.
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公开(公告)号：US20230207697A1
公开(公告)日：2023-06-29
申请号：US17564571
申请日：2021-12-29
发明人： Ruilong Xie , Junli Wang , Brent A. Anderson , Chen Zhang , Heng Wu , Alexander Reznicek
IPC分类号： H01L29/78 , H01L29/08 , H01L29/10 , H01L29/06 , H01L29/66 , H01L23/528 , H01L23/522
CPC分类号： H01L29/7851 , H01L29/0847 , H01L29/1033 , H01L29/0649 , H01L29/66553 , H01L23/5286 , H01L23/5226
摘要： A channel fin extends vertically above a bottom source/drain region, a protective liner is positioned along opposite sidewalls of the bottom source/drain region. The bottom source/drain region is positioned above a semiconductor layer in contact with a first portion of an inner spacer. A first metal layer is positioned between the first portion of the inner spacer and a second portion of the inner spacer, the first portion of the inner spacer partially covers a top surface of the first metal layer and the second portion of the inner spacer substantially covers a bottom surface of the first metal layer for providing a buried power rail. A shallow trench isolation region is positioned above an exposed portion of the first metal layer, the shallow trench isolation region is adjacent to the first portion of the inner spacer, the semiconductor layer, and the bottom source/drain region.
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