公开(公告)号：US20130200467A1

公开(公告)日：2013-08-08

申请号：US13367419

申请日：2012-02-07

申请人： Lisa F. Edge ,  Nathaniel Berliner ,  James John Demarest ,  Balasubramanian S. Haran

发明人： Lisa F. Edge ,  Nathaniel Berliner ,  James John Demarest ,  Balasubramanian S. Haran

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L29/49 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/088 ,  H01L29/66545

摘要： A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors.

摘要翻译： 公开了用于形成双金属填充物的结构和方法以及用于替换栅极金属器件的双阈值电压。 使用涉及钛和铝的选择性沉积方法来形成具有不同填充金属和不同功函数金属的两个相邻晶体管，从而能够在相邻晶体管中实现不同的阈值电压。

公开(公告)号：US08455932B2

公开(公告)日：2013-06-04

申请号：US13102073

申请日：2011-05-06

申请人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Wilfried E. Haensch ,  Balasubramanian S. Haran ,  Pranita Kulkarni

发明人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Wilfried E. Haensch ,  Balasubramanian S. Haran ,  Pranita Kulkarni

IPC分类号： H01L21/336

CPC分类号： H01L27/0207 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/1104 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7834

摘要： A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.

摘要翻译： 采用公共切割掩模来限定栅极图案和局部互连图案，使得局部互连结构和栅极结构相对于彼此形成为零覆盖变化。 局部互连结构可以在第一水平方向上与栅极结构横向间隔开，并且在与第一水平方向不同的第二水平方向上接触另一个栅极结构。 此外，栅极结构可以形成为与邻接栅极结构的局部互连结构共线。 局部互连结构和栅极结构通过公共镶嵌处理步骤形成，使得栅极结构的顶表面和局部互连结构彼此共面。

公开(公告)号：US20130082311A1

公开(公告)日：2013-04-04

申请号：US13609747

申请日：2012-09-11

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7834

摘要： Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.

公开(公告)号：US20130032876A1

公开(公告)日：2013-02-07

申请号：US13195153

申请日：2011-08-01

申请人： Kangguo CHENG ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

发明人： Kangguo CHENG ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795

摘要： A transistor structure includes a channel disposed between a source and a drain; a gate conductor disposed over the channel and between the source and the drain; and a gate dielectric layer disposed between the gate conductor and the source, the drain and the channel. In the transistor structure a lower portion of the source and a lower portion of the drain that are adjacent to the channel are disposed beneath and in contact with the gate dielectric layer to define a sharply defined source-drain extension region. Also disclosed is a replacement gate method to fabricate the transistor structure.

摘要翻译： 晶体管结构包括设置在源极和漏极之间的沟道; 设置在所述通道上并且在所述源极和所述漏极之间的栅极导体; 以及设置在栅极导体和源极之间的栅介质层，漏极和沟道。 在晶体管结构中，源极的下部和与沟道相邻的漏极的下部设置在栅极介电层的下方并与栅极介电层接触以限定明确限定的源 - 漏扩展区。 还公开了制造晶体管结构的替代栅极方法。

公开(公告)号：US20110309333A1

公开(公告)日：2011-12-22

申请号：US12819440

申请日：2010-06-21

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

IPC分类号： H01L29/775 ,  H01L21/34 ,  H01L27/12 ,  H01L21/84

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/2257 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/78696

摘要： A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.

摘要翻译： 提供一种形成半导体器件的方法，其中用于源极和漏极区的掺杂剂从掺杂的介电层引入。 在一个示例中，栅极结构形成在半导体层的厚度小于10nm的SOI衬底的半导体层上。 在与栅极结构相邻的半导体层的至少一部分上形成掺杂介电层。 来自掺杂介电层的掺杂剂被驱动到与栅极结构相邻的半导体层的部分中。 扩散到半导体中的掺杂剂提供了源极和漏极延伸区域。

公开(公告)号：US09214378B2

公开(公告)日：2015-12-15

申请号：US13537141

申请日：2012-06-29

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L21/84 ,  H01L21/762 ,  H01L27/12

CPC分类号： H01L29/0649 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/78 ,  H01L29/7838

摘要： A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

摘要翻译： 制造绝缘体上硅（SOI）半导体器件的方法包括将底切隔离沟槽蚀刻成SOI衬底，所述SOI衬底包括底部衬底，形成在底部衬底上的掩埋氧化物（BOX）层，以及顶部 SOI层，其形成在BOX层上，其中底切隔离沟槽延伸穿过顶部SOI层和BOX层并进入底部衬底，使得底切绝缘沟槽的一部分位于BOX层下方的底部衬底中。 底切隔离槽填充有包括绝缘材料的底切填充物以形成底切隔离区域。 在与底切隔离区相邻的顶部SOI层上形成场效应晶体管（FET）器件，其中底切隔离区延伸在FET的源极/漏极区的下方。

公开(公告)号：US08796128B2

公开(公告)日：2014-08-05

申请号：US13367419

申请日：2012-02-07

申请人： Lisa F. Edge ,  Nathaniel Berliner ,  James John Demarest ,  Balasubramanian S. Haran ,  Raymond J. Donohue

发明人： Lisa F. Edge ,  Nathaniel Berliner ,  James John Demarest ,  Balasubramanian S. Haran ,  Raymond J. Donohue

IPC分类号： H01L21/28 ,  H01L27/088

CPC分类号： H01L29/49 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/088 ,  H01L29/66545

摘要： A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors.

摘要翻译： 公开了用于形成双金属填充物的结构和方法以及用于替换栅极金属器件的双阈值电压。 使用涉及钛和铝的选择性沉积方法来形成具有不同填充金属和不同功函数金属的两个相邻晶体管，从而能够在相邻晶体管中实现不同的阈值电压。

公开(公告)号：US08604539B2

公开(公告)日：2013-12-10

申请号：US13614885

申请日：2012-09-13

申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66795 ,  H01L21/02518 ,  H01L21/02636 ,  H01L21/265 ,  H01L29/66477 ,  H01L29/6681 ,  H01L29/785

摘要： A fin field-effect-transistor fabricated by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate.

公开(公告)号：US08598663B2

公开(公告)日：2013-12-03

申请号：US13108290

申请日：2011-05-16

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/02 ,  H01L29/786 ,  H01L21/70

CPC分类号： H01L27/1203 ,  H01L21/823864 ,  H01L21/823892

摘要： A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.

摘要翻译： 一种半导体结构，其包括绝缘体上半导体（SOI）基板。 SOI衬底包括基极半导体层; 与基底半导体层接触的掩埋氧化物（BOX）层; 以及与BOX层接触的SOI层。 半导体结构还包括相对于SOI层形成的电路，该电路包括在SOI层中具有源极和漏极延伸的N型场效应晶体管（NFET）和栅极; 以及在SOI层中具有源极和漏极延伸的P型场效应晶体管（PFET）和栅极。 每个NFET和PFET下面也可以有一个阱。 存在将非零电偏压施加到SOI衬底。 NFET扩展和PFET扩展中的一个可能分别相对于NFET栅极或PFET栅极被覆盖。

公开(公告)号：US20130307043A1

公开(公告)日：2013-11-21

申请号：US13476567

申请日：2012-05-21

申请人： KANGGUO CHENG ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： KANGGUO CHENG ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L27/088 ,  H01L29/02

CPC分类号： H01L27/1288 ,  H01L21/823431 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1211 ,  H01L28/90

摘要： Capacitors include a first electrical terminal that has fins formed from doped semiconductor on a top layer of doped semiconductor on a semiconductor-on-insulator substrate; a second electrical terminal that has an undoped material having bottom surface shape that is complementary to the first electrical terminal, such that an interface area between the first electrical terminal and the second electrical terminal is larger than a capacitor footprint; and a dielectric layer separating the first and second electrical terminals.

摘要翻译： 电容器包括在绝缘体上半导体衬底上的掺杂半导体的顶层上具有由掺杂半导体形成的鳍片的第一电端子; 第二电端子，其具有与第一电端子互补的底表面形状的未掺杂材料，使得第一电端子和第二电端子之间的界面面积大于电容器覆盖区; 以及分隔第一和第二电端子的电介质层。