公开(公告)号：US06521964B1

公开(公告)日：2003-02-18

申请号：US09386495

申请日：1999-08-30

申请人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

发明人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

IPC分类号： H01L2976

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/82345 ,  H01L29/4933 ,  H01L29/66575 ,  Y10S257/90

摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

摘要翻译： 一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。 本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。 一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。 另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。 另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

公开(公告)号：US06251762B1

公开(公告)日：2001-06-26

申请号：US09458572

申请日：1999-12-09

申请人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

发明人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

IPC分类号： H01L213205

CPC分类号： H01L29/665

摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;M. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

摘要翻译： 一种在0.20微米以下改善多晶硅闸门耐化学性的方法和装置。 本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。 一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。 另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。 另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。 内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。 具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

公开(公告)号：US6020244A

公开(公告)日：2000-02-01

申请号：US777552

申请日：1996-12-30

申请人： Scott E. Thompson ,  Paul A. Packan ,  Tahir Ghani ,  Mark Stettler ,  Shahriar S. Ahmed ,  Mark T. Bohr

发明人： Scott E. Thompson ,  Paul A. Packan ,  Tahir Ghani ,  Mark Stettler ,  Shahriar S. Ahmed ,  Mark T. Bohr

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6659

摘要： An improved well boosting implant which provides better characteristics than traditional halo implants particularly for short channel devices (e.g., 0.25 microns or less). In effect, an implant is distributed across the entire channel with higher concentrations occurring in the center of the channel of the devices having gate lengths less than the critical dimension. This is done by using very large tilt angles (e.g., 30-50.degree.) with a relatively light dopant species and by using a relatively high energy when compared to the traditional halo implants.

摘要翻译： 一种改进的促进良好的植入物，其具有比传统的晕轮植入物更好的特征，特别是对于短通道装置（例如，0.25微米或更小）。 实际上，植入物分布在整个通道上，较高的浓度出现在栅极长度小于临界尺寸的器件的通道的中心。 这通过使用具有相对较轻的掺杂物质的非常大的倾斜角（例如，30-50°）和与传统的晕轮植入物相比使用相当高的能量来完成。

公开(公告)号：US10424580B2

公开(公告)日：2019-09-24

申请号：US13996505

申请日：2011-12-23

申请人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Gopinath Bhimarasetti ,  Tahir Ghani ,  Seiyon Kim

发明人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Gopinath Bhimarasetti ,  Tahir Ghani ,  Seiyon Kim

IPC分类号： H01L29/775 ,  H01L21/02 ,  H01L27/088 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/16 ,  B82Y99/00

摘要： Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.

公开(公告)号：US20180013000A1

公开(公告)日：2018-01-11

申请号：US15528763

申请日：2014-12-24

申请人： Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Gilbert Dewey ,  Nadia M. Rahhal-Orabi ,  Tahir Ghani ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Glenn A. Glass

发明人： Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Gilbert Dewey ,  Nadia M. Rahhal-Orabi ,  Tahir Ghani ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Glenn A. Glass

IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/7853 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/30625 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

摘要： An embodiment includes a microelectronic device comprising: a substrate comprising a raised portion and a non-raised portion, wherein a dielectric material is disposed adjacent the raised portion, an epitaxial sub-fin structure disposed on the raised portion, wherein a bottom portion of the epitaxial sub-fin structure comprises an asymmetric profile, and an epitaxial fin device structure disposed on the sub-fin structure. Other embodiments are described herein.

公开(公告)号：US09583491B2

公开(公告)日：2017-02-28

申请号：US14948083

申请日：2015-11-20

申请人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

发明人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L21/84 ,  H01L29/423 ,  H01L29/10

CPC分类号： H01L21/823821 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/12 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

摘要翻译： 描述了免费的金属氧化物半导体纳米线结构。 例如，半导体结构包括第一半导体器件。 第一半导体器件包括设置在衬底之上的第一纳米线。 第一纳米线具有在衬底上方的第一距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一栅极电极堆叠完全包围第一纳米线的离散通道区域。 半导体结构还包括第二半导体器件。 第二半导体器件包括设置在衬底上方的第二纳米线。 第二纳米线在衬底上方具有第二距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一距离与第二距离不同。 第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。

公开(公告)号：US09240322B2

公开(公告)日：2016-01-19

申请号：US13995171

申请日：2011-12-09

申请人： Jacob M. Jensen ,  Harold W. Kennel ,  Tahir Ghani ,  Robert D. James ,  Mark Y. Liu

发明人： Jacob M. Jensen ,  Harold W. Kennel ,  Tahir Ghani ,  Robert D. James ,  Mark Y. Liu

IPC分类号： H01L21/425 ,  H01L21/268 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L21/2686 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/78

摘要： A pulsed-laser anneal technique includes performing an implant of a selected region of a semiconductor wafer. A co-constituent implant of the selected region is performed, and the pulsed-laser anneal of the selected region performed. A pre-amorphizing implant of the selected region can also be performed. In one embodiment, the implant of the selected region is performed as an insitu implant. In another embodiment, the co-constituent implant is performed as an insitu non-donor implant. In yet another embodiment, the implant and the co-constituent implant of the selected region are performed as an insitu donor and co-constituent implant.

摘要翻译： 脉冲激光退火技术包括执行半导体晶片的选定区域的注入。 执行所选择的区域的共同组成植入物，并且执行所选区域的脉冲激光退火。 还可以进行所选择的区域的非失配植入物。 在一个实施例中，所选择的区域的植入被实施为本体植入物。 在另一个实施例中，辅助植入物作为原位非供体植入物进行。 在另一个实施例中，所选择的区域的植入物和共同构成植入物作为原位供体和共同构成植入物进行。

公开(公告)号：US09153583B2

公开(公告)日：2015-10-06

申请号：US13976074

申请日：2011-12-20

申请人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L21/70 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08

CPC分类号： H01L29/78618 ,  H01L21/76805 ,  H01L21/76886 ,  H01L21/76895 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.

摘要翻译： 公开了用于形成相对于常规器件具有降低的寄生接触电阻的晶体管器件的技术。 在一些示例性实施例中，该技术可以用于实现CMOS器件的MOS晶体管的触点，其中在p型和n型源极/漏极区之间提供中间III-V半导体材料层及其各自的触点 金属显着降低接触电阻。 中间III-V半导体材料层可以具有小的带隙（例如，低于0.5eV）和/或以其它方式被掺杂以提供期望的导电性。 这些技术可以用于许多晶体管架构（例如，平面，鳍状和纳米线晶体管），包括应变和无约束通道结构。

公开(公告)号：US09059024B2

公开(公告)日：2015-06-16

申请号：US13976075

申请日：2011-12-20

申请人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L21/8258 ,  H01L27/06 ,  H01L21/285 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H01L21/768

CPC分类号： H01L27/0922 ,  H01L21/28185 ,  H01L21/28525 ,  H01L21/28575 ,  H01L21/76814 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L23/535 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g.,

摘要翻译： 公开了用于形成低接触电阻晶体管器件的技术。 p型锗层设置在p型源极/漏极区及其各自的接触金属之间，n型III-V半导体材料层设置在n型源极/漏极区及其各自的接触金属之间。 n型III-V族半导体材料层可以具有小的带隙（例如，<0.5eV）和/或以其它方式掺杂以提供期望的导电性，并且p型锗层可以例如用硼掺杂。 在III型V材料沉积在n型源极/漏极区域和锗覆盖的p型源极/漏极区域之后，可以执行回蚀工艺以利用n型和p型之间的高度差 区域自对准接触类型，并在p型区域上露出p型锗，并在n型区域上稀薄n型III-V材料。 这些技术可以用于平面和非平面晶体管架构。

公开(公告)号：US08847281B2

公开(公告)日：2014-09-30

申请号：US13560474

申请日：2012-07-27

申请人： Stephen M. Cea ,  Anand S. Murthy ,  Glenn A. Glass ,  Daniel B. Aubertine ,  Tahir Ghani ,  Jack T. Kavalieros ,  Roza Kotlyar

发明人： Stephen M. Cea ,  Anand S. Murthy ,  Glenn A. Glass ,  Daniel B. Aubertine ,  Tahir Ghani ,  Jack T. Kavalieros ,  Roza Kotlyar

IPC分类号： H01L29/165

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.

摘要翻译： 公开了用于将高迁移率应变通道结合到鳍状晶体管（例如，诸如双栅极，三相等等的FinFET）中的技术，其中应力材料被包覆到鳍的沟道区域上。 在一个示例性实施例中，硅锗（SiGe）被包覆到硅散热片上以提供期望的应力，尽管可以使用其它鳍和包层材料。 这些技术与典型的工艺流程兼容，并且包层沉积可以发生在工艺流程内的多个位置处。 在一些情况下，来自包覆层的内置应力可以通过压缩通道中的鳍和覆层的源极/漏极应力来增强。 在一些情况下，可以提供可选的封盖层以改善栅极电介质/半导体界面。 在一个这样的实施例中，硅被提供在SiGe包覆层上以改善栅极电介质/半导体界面。