公开(公告)号：US07592273B2

公开(公告)日：2009-09-22

申请号：US11737499

申请日：2007-04-19

申请人： Stanley M. Filipiak ,  Zhi-Xiong Jiang ,  Mehul D. Shroff

发明人： Stanley M. Filipiak ,  Zhi-Xiong Jiang ,  Mehul D. Shroff

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L23/3171 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/318 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76829 ,  H01L23/291 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor device comprises providing a portion of a semiconductor device structure, wherein the portion includes a region susceptible to hydrogen incorporation due to subsequent device processing. For example, the subsequent device processing can include one or more of (i) forming a layer over the region, wherein the layer includes hydrogen and (ii) using gases containing hydrogen in a plasma for the subsequent device processing, wherein the semiconductor device is subject to an undesirable device characteristic alteration by hydrogen incorporation into the region. The method further comprises forming a hydrogen barrier layer overlying the region, wherein the hydrogen barrier layer prevents substantial migration of hydrogen made available due to the subsequent device processing into the underlying region. The method further includes performing the subsequent device processing.

摘要翻译： 形成半导体器件的方法包括提供半导体器件结构的一部分，其中该部分包括由于随后的器件处理而容易受氢掺入的区域。 例如，随后的器件处理可以包括以下一个或多个：（i）在该区域上形成层，其中该层包含氢和（ii）使用等离子体中含有氢的气体进行后续的器件处理，其中该半导体器件是 受到氢掺入该区域的不期望的装置特性改变。 所述方法还包括形成覆盖所述区域的氢阻挡层，其中所述氢阻挡层防止由于随后的器件加工而产生的氢的实质迁移进入下面的区域。 该方法还包括执行随后的设备处理。

公开(公告)号：US20080261407A1

公开(公告)日：2008-10-23

申请号：US11737499

申请日：2007-04-19

申请人： Stanley M. Filipiak ,  Zhi-Xiong Jiang ,  Mehul D. Shroff

发明人： Stanley M. Filipiak ,  Zhi-Xiong Jiang ,  Mehul D. Shroff

IPC分类号： H01L21/31

CPC分类号： H01L23/3171 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/318 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76829 ,  H01L23/291 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor device comprises providing a portion of a semiconductor device structure, wherein the portion includes a region susceptible to hydrogen incorporation due to subsequent device processing. For example, the subsequent device processing can include one or more of (i) forming a layer over the region, wherein the layer includes hydrogen and (ii) using gases containing hydrogen in a plasma for the subsequent device processing, wherein the semiconductor device is subject to an undesirable device characteristic alteration by hydrogen incorporation into the region. The method further comprises forming a hydrogen barrier layer overlying the region, wherein the hydrogen barrier layer prevents substantial migration of hydrogen made available due to the subsequent device processing into the underlying region. The method further includes performing the subsequent device processing.

摘要翻译： 形成半导体器件的方法包括提供半导体器件结构的一部分，其中该部分包括由于随后的器件处理而容易受氢掺入的区域。 例如，随后的器件处理可以包括以下一个或多个：（i）在该区域上形成层，其中该层包括氢和（ii）使用等离子体中含有氢气的气体进行随后的器件处理，其中半导体器件是 受到氢掺入该区域的不期望的装置特性改变。 所述方法还包括形成覆盖所述区域的氢阻挡层，其中所述氢阻挡层防止由于随后的器件加工而产生的氢的实质迁移进入下面的区域。 该方法还包括执行随后的设备处理。

公开(公告)号：US06500750B1

公开(公告)日：2002-12-31

申请号：US09609523

申请日：2000-07-03

申请人： Mehul D. Shroff ,  Philip G. Grigg

发明人： Mehul D. Shroff ,  Philip G. Grigg

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76835 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/5258 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/013

摘要： A semiconductor device and its method of formation are disclosed wherein a surface of a semiconductor substrate is planarized to form an interconnect (1244) within a dielectric layer (1243). The top surface of the dielectric layer is then recessed with respect to a top surface of the interconnect to form a step (201). An opaque film (301) is then deposited over the surface of the semiconductor substrate. The opaque film (301) is lithographically patterned and etched, wherein an alignment of the patterning layer (401) is accomplished using topographically discernable features (303) that are formed in the opaque film (301) in regions where the step (201) between the interconnect (1244) and dielectric layer (1243) is produced.

摘要翻译： 公开了半导体器件及其形成方法，其中半导体衬底的表面被平坦化以在电介质层（1243）内形成互连（1244）。 介电层的顶表面然后相对于互连的顶表面凹陷以形成台阶（201）。 然后在半导体衬底的表面上沉积不透明膜（301）。 不透明膜（301）被光刻图案化和蚀刻，其中使用在不透明膜（301）中形成的区域中的形貌可辨别特征（303）来实现图案形成层（401）的对准，其中在步骤（201） 制造互连（1244）和电介质层（1243）。

公开(公告)号：US6154054A

公开(公告)日：2000-11-28

申请号：US309165

申请日：1999-05-10

申请人： Mehul D. Shroff ,  Rajiv Jain ,  Andre Stolmeijer ,  Kathryn E. Gordon

发明人： Mehul D. Shroff ,  Rajiv Jain ,  Andre Stolmeijer ,  Kathryn E. Gordon

IPC分类号： H01L23/525 ,  H03K19/177

CPC分类号： H01L23/5252 ,  H01L23/525 ,  H01L2924/0002

摘要： A field programmable gate array has antifuses disposed over logic modules. Each of these antifuses includes a conductive plug and an overlaying region of programmable material (for example, amorphous silicon). To program one of these antifuses, an electric connection is formed through the programmable material to couple the conductive plug to a metal conductor that overlays the region of programmable material. The metal conductor includes a layer of a barrier metal to separate another metal of the conductor (for example, aluminum from an aluminum layer) from migrating into the programmable material when the antifuse is unprogrammed. In some embodiments, less than three percent of all antifuses of the field programmable gate array has a corner (from the top-down perspective) of the region of programmable material that is disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse. In some embodiments, less than seventy-five percent of all antifuses of the field programmable gate array have an edge of the region of programmable material disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse. Other antifuse structures and methods are also disclosed for preventing programmable material corners and/or edges from compromising yield and/or reliability of programmable devices.

摘要翻译： 现场可编程门阵列具有置于逻辑模块上的反熔丝。 这些反熔丝中的每一个包括导电插塞和可编程材料（例如，非晶硅）的覆盖区域。 为了编程这些反熔丝之一，通过可编程材料形成电连接，以将导电插塞耦合到覆盖可编程材料区域的金属导体。 当反熔丝未编程时，金属导体包括隔离金属层，以将导体的另一金属（例如铝从铝层分离）迁移到可编程材料中。 在一些实施例中，现场可编程门阵列的所有反熔丝的小于3％具有可编程材料区域（在导电插塞的横向距离DIS内）（在金属的下侧视角内）的拐角（在导电插塞的横向距离DIS内） 该反熔丝的导体。 在一些实施例中，现场可编程门阵列的所有反熔丝的小于百分之七十五的边缘都是在该反熔丝的金属导体之下设置（在导电插塞的横向距离DIS内）的可编程材料区域的边缘。 还公开了其他反熔丝结构和方法，用于防止可编程材料拐角和/或边缘损害可编程器件的产量和/或可靠性。

公开(公告)号：US09702925B2

公开(公告)日：2017-07-11

申请号：US14514449

申请日：2014-10-15

申请人： Mark D. Hall ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Steven G. H. Anderson ,  Mehul D. Shroff

IPC分类号： G01R31/26 ,  H01L27/06 ,  G01R31/3181

CPC分类号： G01R31/2632 ,  G01R31/2644 ,  G01R31/31816 ,  H01L27/0629

摘要： A semiconductor device includes a substrate, first electronic circuitry formed on the substrate, a first diode buried in the substrate under the first electronic circuitry, and a first fault detection circuit coupled to the first diode to detect energetic particle strikes on the first electronic circuitry.

公开(公告)号：US09455220B2

公开(公告)日：2016-09-27

申请号：US14292886

申请日：2014-05-31

申请人： Mehul D. Shroff ,  Douglas M Reber ,  Edward O. Travis

发明人： Mehul D. Shroff ,  Douglas M Reber ,  Edward O. Travis

IPC分类号： H01L21/4763 ,  H01L23/522 ,  G06F17/50 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/5283 ,  G06F17/5077 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric current for an interconnect within the integrated circuit device and determining an electromigration stress profile for the interconnect based on the electric current. The method further includes determining an area on the interconnect for placing a stressor to alter the electromigration stress profile for the interconnect.

摘要翻译： 用于选择集成电路装置中用于放置应力源以管理电迁移故障的位置的方法包括计算集成电路装置内的互连的电流，并基于电流确定互连的电迁移应力分布。 该方法还包括确定互连上的区域以放置应力源以改变互连的电迁移应力分布。

公开(公告)号：US09252152B2

公开(公告)日：2016-02-02

申请号：US14228678

申请日：2014-03-28

申请人： Mark D. Hall ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Mehul D. Shroff

IPC分类号： H01L21/338 ,  H01L27/115 ,  H01L21/28 ,  H01L21/306 ,  H01L21/321 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L21/3105

CPC分类号： H01L27/11568 ,  H01L21/31051 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： Forming a semiconductor device in an NVM region and in a logic region using a semiconductor substrate includes forming a dielectric layer and forming a first gate material layer over the dielectric layer. In the logic region, a high-k dielectric and a barrier layer are formed. A second gate material layer is formed over the barrier and the first material layer. Patterning results in gate-region fill material over the NVM region and a logic stack comprising a portion of the second gate material layer and a portion of the barrier layer in the logic region. An opening in the gate-region fill material leaves a select gate formed from a portion of the gate-region fill material adjacent to the opening. A control gate is formed in the opening over a charge storage layer. The portion of the second gate material layer is replaced with a metallic logic gate.

摘要翻译： 在NVM区域和使用半导体衬底的逻辑区域中形成半导体器件包括形成电介质层并在电介质层上形成第一栅极材料层。 在逻辑区域中，形成高k电介质和阻挡层。 在阻挡层和第一材料层之上形成第二栅极材料层。 图案化导致NVM区域上的栅极区域填充材料和包括第二栅极材料层的一部分和逻辑区域中的势垒层的一部分的逻辑堆叠。 栅极填充材料中的开口离开由与开口相邻的栅极 - 区域填充材料的一部分形成的选择栅极。 在电荷存储层上的开口中形成控制栅极。 第二栅极材料层的部分被金属逻辑门替代。

公开(公告)号：US09236344B2

公开(公告)日：2016-01-12

申请号：US14570179

申请日：2014-12-15

申请人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

发明人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

IPC分类号： H01L29/00 ,  H01L23/525 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5258 ,  H01L23/5256 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A back-end-of-line thin ion beam deposited fuse (204) is deposited without etching to connect first and second last metal interconnect structures (110, 120) formed with last metal layers (LM) in a planar multi-layer interconnect stack to programmably connect separate first and second circuit connected to the first and second last metal interconnect structures.

摘要翻译： 在没有蚀刻的情况下沉积后端行的薄离子束沉积的熔丝（204）以将在后面的金属层（LM）形成的第一和第二金属互连结构（110,120）连接在平面多层互连堆叠 以可编程的方式连接连接到第一和第二金属互连结构的单独的第一和第二电路。

公开(公告)号：US09231077B2

公开(公告)日：2016-01-05

申请号：US14195299

申请日：2014-03-03

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/338 ,  H01L29/66 ,  H01L29/40 ,  H01L21/3213

CPC分类号： H01L29/66484 ,  H01L21/28273 ,  H01L21/32139 ,  H01L27/11534 ,  H01L29/401 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833

摘要： A method of forming a semiconductor device includes forming a first gate layer over a substrate in the NVM region and the logic region; forming an opening in the first gate layer in the NVM region; forming a charge storage layer in the opening; forming a control gate over the charge storage layer in the opening; patterning the first gate layer to form a first patterned gate layer portion over the substrate in the logic region and to form a second patterned gate layer portion over the substrate in the NVM region, wherein the second patterned gate layer portion is adjacent the control gate; forming a dielectric layer over the substrate around the first patterned gate layer portion and around the second patterned gate layer portion and the control gate, and replacing the first patterned gate layer portion with a logic gate comprising metal.

摘要翻译： 形成半导体器件的方法包括在NVM区域和逻辑区域中的衬底上形成第一栅极层; 在NVM区域中的第一栅极层中形成开口; 在开口中形成电荷存储层; 在开口中的电荷存储层上形成控制栅极; 图案化第一栅极层以在逻辑区域中的衬底上形成第一图案化栅极层部分，并且在NVM区域中的衬底上形成第二图案化栅极层部分，其中第二图案化栅极层部分与控制栅极相邻; 在所述第一图案化栅极层部分周围以及所述第二图案化栅极层部分和所述控制栅极周围的所述基板上方形成介电层，并用包含金属的逻辑门代替所述第一图案化栅极层部分。

公开(公告)号：US09087913B2

公开(公告)日：2015-07-21

申请号：US13790004

申请日：2013-03-08

申请人： Mark D. Hall ,  Mehul D. Shroff ,  Frank K. Baker, Jr.

发明人： Mark D. Hall ,  Mehul D. Shroff ,  Frank K. Baker, Jr.

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L29/51

CPC分类号： H01L21/82 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11536 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： A thermally-grown oxygen-containing layer is formed over a control gate in an NVM region, and a high-k dielectric layer and barrier layer are formed in a logic region. A polysilicon layer is formed over the oxygen-containing layer and barrier layer and is planarized. A first masking layer is formed over the polysilicon layer and control gate defining a select gate location laterally adjacent the control gate. A second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening at the logic gate location which exposes the barrier layer.

摘要翻译： 在NVM区域的控制栅极上形成热生长含氧层，在逻辑区域形成高k电介质层和阻挡层。 在含氧层和阻挡层上方形成多晶硅层并进行平坦化。 第一掩模层形成在多晶硅层和控制栅极上，该栅极限定了横向邻近控制栅极的选择栅极位置。 形成定义逻辑门位置的第二掩蔽层。 去除多晶硅层的暴露部分，使得选择栅极保留在选择栅极位置处，并且多晶硅部分保持在逻辑门位置。 在选择和控制栅极和多晶硅部分周围形成介电层。 去除多晶硅部分以在逻辑门位置处产生暴露阻挡层的开口。