公开(公告)号：US20170323672A1

公开(公告)日：2017-11-09

申请号：US15604251

申请日：2017-05-24

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Lei Luo

IPC: G11C7/22 ,  G06F13/40 ,  G06F1/08 ,  G06F13/16 ,  G11C7/10 ,  G06F13/42

CPC classification number: G11C7/22 ,  G06F1/08 ,  G06F13/16 ,  G06F13/4068 ,  G06F13/4243 ,  G11C7/1072

Abstract: In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.

公开(公告)号：US20170192912A1

公开(公告)日：2017-07-06

申请号：US15424714

申请日：2017-02-03

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F13/16 ,  G06F1/06 ,  G06F1/10 ,  G11C7/22

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/04 ,  G11C7/222 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US09691447B2

公开(公告)日：2017-06-27

申请号：US14863366

申请日：2015-09-23

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C7/00 ,  G11C7/10 ,  G06F13/16 ,  G06F12/00

CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US20170178702A1

公开(公告)日：2017-06-22

申请号：US15390674

申请日：2016-12-26

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  G11C7/22 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US09257163B2

公开(公告)日：2016-02-09

申请号：US13959633

申请日：2013-08-05

Applicant: Rambus Inc.

Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

IPC: G06F12/00 ,  G11C7/22 ,  G06F13/16 ,  G11C7/02

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/02 ,  G11C7/22

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

Abstract translation: 存储器控制器包括用于接收数据选通信号和对应的读取数据的接口。 数据选通信号和读取数据对应于由存储器控制器发出的读取命令，并且根据数据选通信号和使能信号接收读取的数据。 存储器控制器中的电路是动态地调整使能信号和数据选通信号之间的定时偏移，并且控制逻辑将根据从自由信号发出的最后读取命令以来的时间间隔的确定发出补充读取命令 存储器控制器超过预定值。

公开(公告)号：US20160012869A1

公开(公告)日：2016-01-14

申请号：US14863366

申请日：2015-09-23

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C7/10 ,  G06F13/16

CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US09166583B2

公开(公告)日：2015-10-20

申请号：US14523923

申请日：2014-10-26

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K17/16 ,  H03K19/00 ,  G06F13/40 ,  G11C11/4093 ,  H03K19/0175 ,  G11C11/401 ,  G11C11/419 ,  G11C16/26 ,  G11C11/41 ,  G11C11/4063 ,  G11C11/413

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: In a memory module having an integrated-circuit buffer device coupled to one or more integrated-circuit memory devices, the buffer device receives write data signals from an external control component via a set of data inputs, the write data signals indicating write data to be stored within one or more of the memory devices. Logic within the buffer device sequentially applies controllable termination impedance configurations at the data inputs based on an indication received from the control component and an internal state of the buffer device, applying a first controllable termination impedance configuration at each of the data inputs during a first internal state of the buffer device corresponding to the reception of the write data signals on the data inputs, and applying a second controllable termination impedance configuration at each of the data inputs during a second internal state of the buffer device that succeeds the first internal state.

Abstract translation: 在具有耦合到一个或多个集成电路存储器件的集成电路缓冲器件的存储器模块中，缓冲器件经由一组数据输入从外部控制部件接收写入数据信号，写入数据信号指示写入数据为 存储在一个或多个存储器件中。 缓冲装置内的逻辑基于从控制部件接收到的指示和缓冲装置的内部状态，顺序地在数据输入端施加可控终端阻抗配置，在第一内部的每个数据输入端施加第一可控终端阻抗配置 所述缓冲器装置的状态与所述数据输入上的所述写数据信号的接收相对应，以及在所述第一内部状态的所述缓冲器件的第二内部状态期间，在每个所述数据输入端施加第二可控终端阻抗配置。

公开(公告)号：US09165617B2

公开(公告)日：2015-10-20

申请号：US14153822

申请日：2014-01-13

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C7/00 ,  G11C7/10 ,  G06F13/16 ,  G06F12/00

CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

Abstract translation: 具有时间交错请求信号输出的存储器控​​制器。 产生第一定时信号，同时产生具有相对于第一定时信号的第一相位差的第二定时信号。 响应于第一定时信号发送地址值，响应于构成第一存储器访问请求的第二定时信号，地址值和控制值发送控制值。

公开(公告)号：US20150263733A1

公开(公告)日：2015-09-17

申请号：US14728917

申请日：2015-06-02

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K19/0175 ,  G11C11/4093 ,  H03K19/00

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: A memory controller transmits a plurality of control values to a non-volatile memory device together with one or more programming commands. The plurality of control values include (i) a first control value that specifies a first termination resistance to be applied to an I/O node of the non-volatile memory device during an interval in which a first data signal transmitted on a bidirectional signaling line coupled to the I/O node is to be received within the non-volatile memory device and (ii) a second control value that specifies a second termination resistance to be applied to the I/O node during an interval in which a second data signal is transmitted on the bidirectional signaling line by another non-volatile memory device.

Abstract translation: 存储器控制器与一个或多个编程命令一起将多个控制值发送到非易失性存储器件。 多个控制值包括：（i）第一控制值，其指定在双向信令线路中发送的第一数据信号的间隔期间应用于非易失性存储器件的I / O节点的第一终端电阻 耦合到所述I / O节点的所述I / O节点将被接收在所述非易失性存储器设备内;以及（ii）第二控制值，其指定在所述I / O节点期间施加的第二终端电阻， 在双向信令线路上由另一非易失性存储器件发送。

公开(公告)号：US20150244364A1

公开(公告)日：2015-08-27

申请号：US14711538

申请日：2015-05-13

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K19/00 ,  G11C11/4093 ,  G11C11/419 ,  H03K19/0175

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: A non-volatile memory device determines, based at least partly on a first multi-bit device address received via a signaling interface and an incoming chip-select signal, whether the device is to participate in a memory access transaction by receiving or outputting data via an I/O node of the signaling interface. Based at least in part on that determination, on-die termination circuitry within the non-volatile memory device switchably couples or decouples a termination resistance between the I/O node and a supply voltage node during a data transmission phase of the memory access transaction.

Abstract translation: 至少部分地基于经由信令接口和输入芯片选择信号接收到的第一多位设备地址来确定设备是否通过接收或输出数据来参与存储器访问事务，非易失性存储器设备 信令接口的I / O节点。 至少部分地基于该确定，在存储器访问事务的数据传输阶段期间，非易失性存储器件内的片上终端电路可切换地将I / O节点和电源电压节点之间的终端电阻耦合或去耦。