中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

200 records (took 0.049 seconds)

    System and method for dark field inspection
    71.
    发明授权
    System and method for dark field inspection 有权
    暗场检查系统和方法

    公开(公告)号：US09134633B2

    公开(公告)日：2015-09-15

    申请号：US14138743

    申请日：2013-12-23

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Bo-Jiun Lin ,  Hsin-Chieh Yao ,  Hai-Ching Chen ,  Tien-I Bao

    IPC: G03F9/00 ,  H01L21/66 ,  G01N21/88 ,  H01L21/027 ,  G01N21/956

    CPC classification number: G03F9/7069 ,  G01N21/8806 ,  G01N21/956 ,  G01N2021/8822 ,  G01N2021/8825 ,  G01N2021/95676 ,  G01N2201/061 ,  G01N2201/06113 ,  G03F7/70633 ,  H01L21/027 ,  H01L22/12 ,  H01L22/20

    Abstract: The present disclosure provides a method for fabricating a semiconductor structure. The method comprises providing a substrate and a patterned layer formed on the substrate, one or more overlay marks being formed on the patterned layer; performing a pre-film-formation overlay inspection using a bright field (BF) inspection tool to receive a pre-film-formation data on the one or more overlay marks on the patterned layer; forming one or more layers on the patterned layer; performing a post-film-formation overlay inspection using a dark field (DF) inspection tool to receive a post-film-formation data on the one or more overlay marks underlying the one or more layers; and determining whether the pre-film-formation data matches the post-film-formation data.

    Abstract translation: 本公开提供了一种用于制造半导体结构的方法。 该方法包括提供衬底和形成在衬底上的图案层，在图案化层上形成一个或多个覆盖标记; 使用亮场（BF）检查工具进行预膜形成覆盖检查，以在图案化层上的一个或多个覆盖标记上接收预成膜数据; 在所述图案化层上形成一层或多层; 使用暗场（DF）检查工具进行后期成膜覆盖检查，以接收关于所述一个或多个层下面的一个或多个覆盖标记的后期成膜数据; 以及确定成膜前数据是否与成膜后数据相匹配。

    Lithography Using High Selectivity Spacers for Pitch Reduction
    74.
    发明申请
    Lithography Using High Selectivity Spacers for Pitch Reduction 有权
    使用高选择性间隔的光刻技术进行减径

    公开(公告)号：US20150155171A1

    公开(公告)日：2015-06-04

    申请号：US14096864

    申请日：2013-12-04

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Yu-Sheng Chang ,  Chung-Ju Lee ,  Cheng-Hsiung Tsai ,  Yung-Hsu Wu ,  Hsiang-Huan Lee ,  Hai-Ching Chen ,  Ming-Feng Shieh ,  Tien-I Bao ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Shau-Lin Shue

    IPC: H01L21/033

    CPC classification number: H01L21/0338 ,  H01L21/02186 ,  H01L21/02282 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/32139

    Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

    Abstract translation: 用于图案化半导体器件的方法实施例包括在硬掩模上构图虚拟层以形成一个或多个虚拟线。 侧壁对齐的间隔件在一个或多个虚线和硬掩模上顺应地形成。 第一反向材料层形成在侧壁对齐的间隔物上。 在第一反向材料层上形成并图案化第一光致抗蚀剂。 使用第一光致抗蚀剂作为掩模的第一反向材料层，其中侧壁对齐的间隔物不被蚀刻。 去除一个或多个虚拟线，并且使用侧壁对准的间隔件和第一反向材料层作为掩模来对硬掩模进行图案化。 用于形成侧壁对准间隔物的材料比用于形成第一反向材料层的材料具有更高的选择性。

    Semiconductor Integrated Circuit and Fabricating the Same
    75.
    发明申请
    Semiconductor Integrated Circuit and Fabricating the Same 有权
    半导体集成电路和制造相同

    公开(公告)号：US20140346675A1

    公开(公告)日：2014-11-27

    申请号：US14459500

    申请日：2014-08-14

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Hsin-Yen Huang ,  Yu-Sheng Chang ,  Hai-Ching Chen ,  Tien-I Bao

    IPC: H01L23/532 ,  H01L23/528

    CPC classification number: H01L23/5329 ,  H01L21/7682 ,  H01L21/76835 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor integrated circuit (IC) with a dielectric matrix is disclosed. The dielectric matrix is located between two conductive features. The matrix includes a first nano-scale dielectric block, a second nano-scale dielectric block, and a first nano-air-gap formed by a space between the first nano-scale dielectric block and the second nano-scale dielectric block. The matrix also includes third nano-scale dielectric block and a second nano-air-gap formed by a space between the second nano-scale dielectric block and the third nano-scale dielectric block. The nano-scale dielectric blocks share a first common width, and the nano-air-gaps share a second common width. An interconnect structure integrates the dielectric matrix with the conductive features.

    Abstract translation: 公开了一种具有介质矩阵的半导体集成电路（IC）。 电介质矩阵位于两个导电特征之间。 该基质包括第一纳米尺度介电块，第二纳米尺度介电块和由第一纳米尺度介电块和第二纳米尺度介电块之间的空间形成的第一纳米气隙。 该基质还包括由第二纳米尺度介电块和第三纳米级介电块之间的空间形成的第三纳米尺度介电块和第二纳米气隙。 纳米级介质块共享第一共同宽度，并且纳米气隙共享第二共同宽度。 互连结构将介电矩阵与导电特征相结合。

    Schemes for Forming Barrier Layers for Copper in Interconnect Structures
    76.
    发明申请
    Schemes for Forming Barrier Layers for Copper in Interconnect Structures 审中-公开
    在互连结构中形成铜屏障层的方案

    公开(公告)号：US20140231999A1

    公开(公告)日：2014-08-21

    申请号：US14263842

    申请日：2014-04-28

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

    IPC: H01L23/532

    CPC classification number: H01L23/53238 ,  H01L21/322 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

    Abstract translation: 形成半导体结构的方法包括提供基板; 在衬底上形成低k电介质层; 将导电布线嵌入到低k电介质层中; 并且将导电布线热浸在含碳硅烷类化学品中以在导电布线上形成阻挡层。 在用于嵌入导电布线的开口中形成衬里阻挡层。 衬里阻挡层可以包括与阻挡层相同的材料，并且衬里阻挡层可以在形成阻挡层之前被凹入，并且可以包含可以被硅化的金属。

    Semiconductor Integrated Circuit and Fabricating the Same
    78.
    发明申请
    Semiconductor Integrated Circuit and Fabricating the Same 有权
    半导体集成电路和制造相同

    公开(公告)号：US20140203434A1

    公开(公告)日：2014-07-24

    申请号：US13744781

    申请日：2013-01-18

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Hsin-Yen Huang ,  Yu-Sheng Chang ,  Hai-Ching Chen ,  Tien-I Bao

    IPC: H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/5329 ,  H01L21/7682 ,  H01L21/76835 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a precursor. A decomposable polymer layer (DPL) is deposited between the conductive features of the precursor. The DPL is annealed to form an ordered periodic pattern of different types of polymer nanostructures. One type of polymer nanostructure is decomposed by a first selectively to form a trench. The trench is filled by a dielectric layer to form a dielectric block. The remaining types of polymer nanostructures are decomposed by a second selectively etching to form nano-air-gaps.

    Abstract translation: 公开了制造半导体集成电路（IC）的方法。 该方法包括接收前体。 可分解的聚合物层（DPL）沉积在前体的导电特征之间。 DPL被退火以形成不同类型的聚合物纳米结构的有序周期性图案。 一种类型的聚合物纳米结构被选择性地分解以形成沟槽。 沟槽由介电层填充以形成介质块。 剩余的聚合物纳米结构类型通过第二选择性蚀刻分解以形成纳米气隙。

Patent Agency Ranking