公开(公告)号：US20080311744A1

公开(公告)日：2008-12-18

申请号：US12198602

申请日：2008-08-26

申请人： Nicholas C.M. Fuller ,  Stephen McConnell Gates ,  Timothy J. Dalton

发明人： Nicholas C.M. Fuller ,  Stephen McConnell Gates ,  Timothy J. Dalton

IPC分类号： H01L21/768

CPC分类号： H01L21/0331 ,  H01L21/76811 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/12576 ,  Y10T428/12611 ,  Y10T428/31667 ,  H01L2924/00

摘要： Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.

摘要翻译： 具有用于90nm以上的有机硅酸盐玻璃基材料的互连结构，其中描述了使用线路优先方法的多层硬掩模的BEOL技术。 本发明的互连结构实现了相应的改进的器件/互连性能，并且由于不暴露OSG材料以抵抗去除等离子体以及由于交替的无机/有机多层硬掩模堆叠而提供了实质的双镶嵌工艺窗口。 后一特征意味着对于在特定蚀刻步骤期间被蚀刻的每个无机层，该领域中相应的图案转移层是有机的，反之亦然。

公开(公告)号：US20080286972A1

公开(公告)日：2008-11-20

申请号：US12170634

申请日：2008-07-10

申请人： Timothy J. Dalton ,  Wesley C. Natzle ,  Paul W. Pastel ,  Richard S. Wise ,  Hongwen Yan ,  Ying Zhang

发明人： Timothy J. Dalton ,  Wesley C. Natzle ,  Paul W. Pastel ,  Richard S. Wise ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/308

CPC分类号： H01L21/32139 ,  H01L21/32137 ,  Y10S438/909

摘要： A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.

摘要翻译： 一种用于在半导体晶片上提供均匀且一致的栅叠层蚀刻的化学组成和方法，由此所述组合物包括添加的蚀刻剂和添加的压载气体。 使用这种组合的蚀刻剂和压载气组合物形成栅堆叠。 压载气体可以类似于或等同于在处理室内产生的气态副产物。 压载气体以过载量或足以补偿横跨水的变化因子变化的量加入。 这种蚀刻剂和添加的压载气体在整个晶片上形成基本均匀的蚀刻剂，从而适应或补偿这些图案因子差异。 当使用这种均匀的蚀刻剂蚀刻晶片时，在暴露的晶片表面上形成钝化层。 钝化层在蚀刻期间保护栅极堆叠的侧壁以产生更直的栅叠层。

公开(公告)号：US20080283964A1

公开(公告)日：2008-11-20

申请号：US12144229

申请日：2008-06-23

申请人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Nicholas C. Fuller ,  Louis C. Hsu

发明人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Nicholas C. Fuller ,  Louis C. Hsu

IPC分类号： H01L23/525 ,  H01L21/44

CPC分类号： H01L23/5252 ,  H01L21/76843 ,  H01L21/76844 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.

摘要翻译： 提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。 根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。 当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。 也可以通过增加局部温度来加速相邻互连之间的电阻的降低。

公开(公告)号：US20080045011A1

公开(公告)日：2008-02-21

申请号：US11506227

申请日：2006-08-18

申请人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

IPC分类号： H01L21/44

CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/28123

摘要： A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.

公开(公告)号：US07298935B1

公开(公告)日：2007-11-20

申请号：US11415923

申请日：2006-05-01

申请人： Charles T. Black ,  Gian-Luca Bona ,  Timothy J. Dalton ,  Nicholas C. M. Fuller ,  Roland Germann ,  Maurice McGlashan-Powell ,  Chandrasekhar Narayan ,  Robert L. Sandstrom

发明人： Charles T. Black ,  Gian-Luca Bona ,  Timothy J. Dalton ,  Nicholas C. M. Fuller ,  Roland Germann ,  Maurice McGlashan-Powell ,  Chandrasekhar Narayan ,  Robert L. Sandstrom

IPC分类号： G02B6/00

CPC分类号： G02B6/126 ,  B29D11/00759 ,  G02B6/136 ,  G02B2006/1215

摘要： A method in effectuating the redirection of light which is propagated within a waveguide, and which eliminates the necessity for a bending of the waveguide, or the drawbacks encountered in directional changes in propagated light involving the need for sharp curves of essentially small-sized radii, which would resultingly lead to excessive losses in light. In this connection, the method relates to the fabricating and the provision of a wire-grid polarization beam splitter within an optical waveguide, which utilizes a diblock copolymer template to formulate the wire-grid.

摘要翻译： 实现在波导内传播的光的重定向并且消除波导的弯曲的必要性的方法或者涉及需要基本上小的半径的尖锐曲线的传播光的方向性变化中遇到的缺点， 这将导致轻微的过度损失。 在这方面，该方法涉及在光波导内制造和提供线栅偏振分束器，其利用二嵌段共聚物模板来配制线栅。

公开(公告)号：US07253116B2

公开(公告)日：2007-08-07

申请号：US10904608

申请日：2004-11-18

申请人： Nicholas C. M. Fuller ,  Timothy J. Dalton

发明人： Nicholas C. M. Fuller ,  Timothy J. Dalton

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76802 ,  G03F7/427 ,  H01L21/31138

摘要： A high ion energy and high pressure O2/CO-based plasma for ashing field photoresist material subsequent to via-level damascene processing. The optimized plasma ashing process is performed at greater than approximately 300 mT pressure and ion energy greater than approximately 500 W conditions with an oxygen partial pressure of greater than approximately 85%. The rapid ash rate of the high pressure/high ion energy process and minimal dissociation conditions (no “source” power is applied) allow minimal interaction between the interlevel dielectric and ash chemistry to achieve minimal overall sidewall modification of less than approximately 5 nm.

摘要翻译： 用于经过层级镶嵌处理之后灰化场致光材料的高离子能量和高压O 2 2 / CO基等离子体。 优化的等离子体灰化过程在大于约300mT的压力下进行，离子能量大于约500W条件，氧分压大于约85％。 高压/高离子能量过程的快速灰分速率和最小解离条件（不施加“源”功率）允许层间电介质和灰分化学之间的最小相互作用，以实现小于约5nm的最小总体侧壁修饰。

公开(公告)号：US07223691B2

公开(公告)日：2007-05-29

申请号：US10965031

申请日：2004-10-14

申请人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Patrick W. DeHaven ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Terry A. Spooner ,  Tsong-Lin L. Tai ,  Kwong Hon Wong ,  Chin-Chao Yang

发明人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Patrick W. DeHaven ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Terry A. Spooner ,  Tsong-Lin L. Tai ,  Kwong Hon Wong ,  Chin-Chao Yang

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76888

摘要： A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.

摘要翻译： 具有低接触电阻和改进的可靠性的新颖的层间接触通孔结构以及形成接触通孔的方法。 该方法包括以下步骤：通过层间电介质层蚀刻开口以暴露下面的金属（铜）层表面; 并且将惰性气体（氮气）的低能量离子注入进入下面暴露的金属; 并且将耐火衬垫沉积到壁和底部通孔结构中，由于进行的惰性气体注入的存在而将具有较低的接触电阻。 优选地，惰性氮气与下面暴露的铜金属反应形成一层薄的CuN。

公开(公告)号：US07064064B2

公开(公告)日：2006-06-20

申请号：US11058783

申请日：2005-02-16

申请人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

摘要翻译： 公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。 互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

公开(公告)号：US07001835B2

公开(公告)日：2006-02-21

申请号：US10707119

申请日：2003-11-21

申请人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik A. Kumar ,  Stephen M. Rossnagel ,  Andrew H. Simon ,  Douglas C. La Tulipe, Jr.

发明人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik A. Kumar ,  Stephen M. Rossnagel ,  Andrew H. Simon ,  Douglas C. La Tulipe, Jr.

IPC分类号： H01L21/4763

CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2855 ,  H01L21/76841 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 μOhm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.

摘要翻译： 集成电路后端的硬掩模层由具有小于50％Ta且电阻率大于400μΩ-cm的组成的TaN形成，使得其在可见光中基本上是透明的并且允许上和 通过硬掩模和ILD的中间层降低对准标记。 形成硬掩模的优选方法是通过在含有N 2 O 2的环境中溅射沉积Ta并使流速使得（N 2 N 2 O 2）/（N _{2 +载体流）> 0.5。}

公开(公告)号：US06933191B2

公开(公告)日：2005-08-23

申请号：US10605260

申请日：2003-09-18

申请人： Glenn A. Biery ,  Zheng G. Chen ,  Timothy J. Dalton ,  Naftali E. Lustig

发明人： Glenn A. Biery ,  Zheng G. Chen ,  Timothy J. Dalton ,  Naftali E. Lustig

IPC分类号： H01L21/02 ,  H01L21/027 ,  H01L21/20 ,  H01L21/8242

CPC分类号： H01L28/20 ,  H01L21/0274 ,  H01L28/40

摘要： MIM capacitors and thin film resistors are fabricated with at least one less lithographic step than the prior art methods. The process step reduction is realized by using semi-transparent metallic electrodes, fabricated with a two-mask process, which provides for direct alignment, and eliminates the need for alignment trenches in an additional layer.

摘要翻译： MIM电容器和薄膜电阻器与现有技术的方法相比制造的光刻步骤至少少一个。 通过使用通过双掩模工艺制造的半透明金属电极实现工艺步骤减少，其提供直接对准，并且不需要在附加层中对准沟槽。