公开(公告)号：US20180082722A1

公开(公告)日：2018-03-22

申请号：US15809647

申请日：2017-11-10

Applicant: Intel Corporation

Inventor： Pramod Kolar ,  John Riley ,  Gunjan Pandya

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/10 ,  G11C7/1096 ,  G11C7/22

Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.

公开(公告)号：US20180075917A1

公开(公告)日：2018-03-15

申请号：US15445987

申请日：2017-03-01

Applicant: Toshiba Memory Corporation

Inventor： Yuko UTSUNOMIYA ,  Takahiro SHIMIZU ,  Yoshihiko SHINDO ,  Akio SUGAHARA ,  Toshio YAMAMURA

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G06F3/06 ,  G06F11/14

CPC classification number: G11C16/3459 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/067 ,  G06F11/1451 ,  G06F11/1469 ,  G06F2201/84 ,  G11C7/1048 ,  G11C7/1087 ,  G11C7/1096 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/20

Abstract: A semiconductor memory device includes memory cells, a sense amplifier unit including a first latch circuit, and a control unit configured to execute read and write operations on the memory cells. The control unit, while executing the write operation on the memory cells, responsive to a write suspend command followed by a read command, performs a data saving operation, the read operation, and a data restoring operation prior to resuming the write operation. The data saving operation includes transferring first data stored in the first latch circuit to an external device, the first data including at least a result of verify operation performed on the memory cells. The data restoring operation includes transferring the first data to the first latch circuit.

公开(公告)号：US20180075893A1

公开(公告)日：2018-03-15

申请号：US15449198

申请日：2017-03-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumiyoshi MATSUOKA

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C7/1096 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/79 ,  G11C2213/82

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing one of first and second data, first and second lines coupled to the first memory cell, a first controller capable of simultaneously outputting first and second signals, and a first driver configured to apply a first voltage to the first line and apply a second voltage to the second line according to the first data and an asserted first signal in the first data writing, and apply a third voltage to the first line and apply a fourth voltage to the second line according to the second data and an asserted second signal in the second data writing.

公开(公告)号：US20180068698A1

公开(公告)日：2018-03-08

申请号：US15612150

申请日：2017-06-02

Applicant: SK hynix Inc.

Inventor： Seol Hee LEE ,  Chang Hyun KIM ,  Dae Yong SHIM ,  Kang Seol LEE

IPC: G11C7/22 ,  G11C7/06 ,  G11C7/12 ,  G11C7/10 ,  G11C8/12 ,  G06F11/10

CPC classification number: G11C7/222 ,  G06F11/108 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1063 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/12 ,  G11C2029/0411

Abstract: A semiconductor device includes an internal operation control circuit suitable for generating a set period signal which is enabled for a set period, in response to a write command and an internal operation control signal, and generating a column select signal, an output control signal and an input control signal in response to the set period signal; and an internal operation circuit suitable for performing an internal operation of converting parity data generated from input data and storing the converted parity data in a memory cell array, in response to the column select signal, the output control signal and the input control signal.

公开(公告)号：US20170372794A1

公开(公告)日：2017-12-28

申请号：US15628593

申请日：2017-06-20

Applicant: Darryl G. Walker

Inventor： Darryl G. Walker

IPC: G11C29/12 ,  G11C7/22 ,  H01L29/78

CPC classification number: G11C29/12 ,  G11C7/04 ,  G11C7/065 ,  G11C7/1045 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C8/08 ,  G11C11/419 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/14 ,  G11C29/16 ,  G11C29/46 ,  G11C29/48 ,  G11C29/50016 ,  G11C2029/0409 ,  G11C2029/1202 ,  G11C2029/5002 ,  G11C2029/5004 ,  H01L29/78

Abstract: A semiconductor device that has a normal mode of operation and a test mode of operation and can include: a first circuit that generates at least one assist signal having an assist enable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell of the semiconductor device as compared to read or write operations when the assist signal has an assist disable logic level; and the first circuit generates the at least one assist signal having the assist disable logic level in the test mode of operation

公开(公告)号：US09842627B2

公开(公告)日：2017-12-12

申请号：US15438567

申请日：2017-02-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jonathan Tsung-Yung Chang ,  Cheng-Hung Lee ,  Chi-Ting Cheng ,  Hung-Jen Liao ,  Jhon-Jhy Liaw ,  Yen-Huei Chen

IPC: G11C8/00 ,  G11C5/02 ,  G11C5/14 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/14 ,  G11C7/10 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/417

Abstract: A device includes a first strap cell, a first data line, and a second data line. The first strap cell is arranged between a first row of memory cells and a second row of memory cells in a memory array. A first portion of the first data line is configured to transmit data to or from a first memory cell in the first row of memory cells. The second data line and a second portion of the first data line are configured to transmit data to or from a second memory cell in the second row of memory cells.

公开(公告)号：US09779802B1

公开(公告)日：2017-10-03

申请号：US15199662

申请日：2016-06-30

Applicant: National Tsing Hua University

Inventor： Meng-Fan Chang ,  Yi-Ju Chen

IPC: G11C11/419 ,  G11C7/10 ,  G11C7/14 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C7/1048 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/14

Abstract: A write assist circuit includes a write detection circuit, a write detection-aware write driver and a write condition recovery circuit. The write detection circuit receives a detected result signal and a write data, and generates a write detect control signal and generating a selecting signal according to the detection result signal and the write data. The write detection-aware write driver receives the write detect control signal and operates a write detection operation on a selected memory cell according to the write detect control signal, and decides whether to provide a negative voltage to one of a bit line and an inverted bit line of the selected memory cell or not according to the selecting signal. The write condition recovery circuit respectively couples the bit line and the inverted bit line to the write data line and the inverted data line according to a write pass-gate control signal, and provides a pre-charge voltage to the write data line and the inverted data line during the write detection time period according to a recovery signal.

公开(公告)号：US09768174B2

公开(公告)日：2017-09-19

申请号：US15210068

申请日：2016-07-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: G11C11/04 ,  H01L27/105 ,  H01L29/786 ,  H01L27/12 ,  G11C5/06 ,  G11C7/06 ,  G11C7/12 ,  G11C11/404

CPC classification number: H01L27/1052 ,  G11C5/06 ,  G11C7/062 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/16 ,  G11C8/16 ,  G11C11/4045 ,  G11C11/405 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/7869

Abstract: A semiconductor device for efficiently compressing a large volume of image data is provided. The semiconductor device includes a memory cell array, an analog processing circuit, a writing circuit, and a row driver, whereby highly efficient compressing of image data can be performed. A first current corresponding to first data and a second current corresponding to one of a plurality of second data that is a target for comparison with the first data are generated in the writing circuit. A differential current between the first current and the second current is supplied to the analog processing circuit, so that the first data and the plurality of second data are compared. Accordingly, a piece of the second data that has the same content as the first data is detected, and a displacement from the first data to the second data can be calculated.

公开(公告)号：US20170255387A1

公开(公告)日：2017-09-07

申请号：US15277159

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Kuljit S. Bains ,  James A. McCall

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/16 ,  G11C7/10 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/4076 ,  G11C2207/2263 ,  G11C2207/229

Abstract: Examples include techniques to cause a content pattern to be stored to memory cells of a memory device. Example techniques include forwarding a content pattern to a memory device for storage to registers maintained at the memory device. A command is generated and forwarded to the memory device to cause the content pattern to be stored to at least a portion of memory cells for the memory device responsive to a write request to the memory device having a matching content pattern.

公开(公告)号：US20170200485A1

公开(公告)日：2017-07-13

申请号：US15159369

申请日：2016-05-19

Applicant: SK hynix Inc.

Inventor： Geun Ho CHOI

IPC: G11C7/22 ,  G11C7/12 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/225 ,  G11C2207/229

Abstract: A semiconductor device may include a strobe signal buffer, a strobe signal division circuit, and a drive control circuit. The strobe signal buffer may buffer a first data strobe signal and a second data strobe signal to generate a buffer output signal and an inverted buffer output signal. The strobe signal division circuit may divide the buffer output signal and the inverted buffer output signal to generate internal strobe signals which are used in capturing data when receiving data. The drive control circuit may drive the buffer output signal to a predetermined logic level during an initial section of time from a point of time when a write operation is performed.