公开(公告)号：US06797560B2

公开(公告)日：2004-09-28

申请号：US09859513

申请日：2001-05-18

申请人： Keizo Hosoda ,  Yusuke Muraki

发明人： Keizo Hosoda ,  Yusuke Muraki

IPC分类号： H01L218242

CPC分类号： H01L21/02356 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31604 ,  H01L28/40

摘要： A tantalum oxide film is formed on a lower conductive film by vapor-deposition, and then is treated with active oxygen species. The treated film is annealed at a temperature lower than the crystallization temperature of tantalum oxide by 10 to 80° C. in an inert atmosphere. Subsequently, an upper conductive film is formed on the annealed tantalum oxide film.

摘要翻译： 通过气相沉积在下导电膜上形成氧化钽膜，然后用活性氧物质处理。 在惰性气氛下，将处理过的膜在比氧化钽的结晶温度低的温度下退火10〜80℃。 随后，在退火的氧化钽膜上形成上导电膜。

公开(公告)号：US06787371B2

公开(公告)日：2004-09-07

申请号：US10397315

申请日：2003-03-27

申请人： Tatsuo Sawasaki

发明人： Tatsuo Sawasaki

IPC分类号： H01L2100

CPC分类号： C23C14/5813 ,  H01L21/02197 ,  H01L21/02282 ,  H01L21/02354 ,  H01L21/02356 ,  H01L21/31604 ,  H01L21/31691 ,  H01L21/76838 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： In a method of forming a ferroelectric film according to the present invention, pulsed laser light or pulsed lamp light is applied to an amorphous oxide film formed over a substrate to form microcrystalline nuclei of oxide in the film. Crystallization of the oxide is performed by applying pulsed laser light or pulsed lamp light to the film including the microcrystalline nuclei to form the ferroelectric film.

摘要翻译： 在根据本发明的形成铁电体膜的方法中，将脉冲激光或脉冲灯光施加到形成在衬底上的非晶氧化物膜，以在膜中形成氧化物的微晶核。 通过对包含微晶核的膜施加脉冲激光或脉冲灯光来进行氧化物的结晶，形成铁电体膜。

公开(公告)号：US06759310B2

公开(公告)日：2004-07-06

申请号：US10067486

申请日：2002-02-04

申请人： Hiroshi Tayanaka

发明人： Hiroshi Tayanaka

IPC分类号： H01L2130

CPC分类号： C30B25/18 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/02381 ,  H01L21/02502 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/31695 ,  H01L21/76259 ,  H01L29/16 ,  H01L29/20

摘要： A semiconductor substrate includes a porous semiconductor having: a porous layer, with an impurity concentration on varying in the depth direction, or having a porous semiconductor containing an impurity with a content of 1×1018cm−3 or more, or provided by pore formation in an epitaxial growth layer. A method of making a semiconductor substrate; includes forming a variant impurity layer with an impurity concentration varying in the depth direction on one surface of a supporting substrate, and converting the variant impurity layer into a porous layer having a variant porosity in the depth direction. A method of making a thin-film semiconductive member; includes forming a semiconductive thin film on the supporting substrate and separating it by cleavage in the porous phase, in addition to the method for making the semiconductor substrate.

摘要翻译： 半导体衬底包括多孔半导体，其具有：具有在深度方向上变化的杂质浓度的多孔层，或具有含有1×10 18 cm -3以上的杂质的多孔半导体，或者设置 通过外延生长层中的孔形成。 一种制造半导体衬底的方法; 包括在支撑衬底的一个表面上形成具有在深度方向上变化的杂质浓度的变体杂质层，并将该变体杂质层转换成在深度方向上具有变异孔隙率的多孔层。 制造薄膜半导体元件的方法; 包括在支撑衬底上形成半导体薄膜，并且除了制备半导体衬底的方法之外，通过在多孔相中的切割分离半导体薄膜。

公开(公告)号：US20040092107A1

公开(公告)日：2004-05-13

申请号：US10686333

申请日：2003-10-14

发明人： Jerome M. Eldridge

IPC分类号： H01L021/302 ,  H01L021/461

CPC分类号： H01L21/02197 ,  H01L21/02244 ,  H01L21/02356 ,  H01L21/3162 ,  H01L21/31662 ,  H01L21/31683 ,  H01L21/31691

摘要： A method includes forming a material over a substrate, oxidizing the material, and separately from the oxidizing, converting at least a portion of the oxidized material to a perovskite-type crystalline structure. The material can include an alloy material containing at least two metals. The method can further include retarding interdiffusion of the two metals. Such methods exhibit substantial advantage when at least two of the metals exhibit a substantial difference in chemical affinity for oxygen. A passivation layer against carbon and nitrogen reaction can be provided over the material. The passivation layer can be oxidized into a dielectric layer. The perovskite-type material can also be a dielectric layer.

摘要翻译： 一种方法包括在衬底上形成材料，氧化材料，并与氧化分开，将至少一部分氧化材料转化为钙钛矿型晶体结构。 该材料可以包括含有至少两种金属的合金材料。 该方法还可以包括延缓两种金属的相互扩散。 当至少两种金属表现出对氧的化学亲和力的实质差异时，这种方法表现出显着的优点。 可以在材料上提供抵抗碳和氮反应的钝化层。 钝化层可被氧化成电介质层。 钙钛矿型材料也可以是电介质层。

公开(公告)号：US06720603B2

公开(公告)日：2004-04-13

申请号：US10321614

申请日：2002-12-18

申请人： Shinpei Iijima ,  Yuzuru Ohji ,  Masato Kunitomo ,  Masahiko Hiratani ,  Yuichi Matsui ,  Hiroyuki Ohta ,  Yukihiro Kumagai

发明人： Shinpei Iijima ,  Yuzuru Ohji ,  Masato Kunitomo ,  Masahiko Hiratani ,  Yuichi Matsui ,  Hiroyuki Ohta ,  Yukihiro Kumagai

IPC分类号： H01L27108

CPC分类号： H01L21/02183 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/31637 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/91

摘要： A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.

摘要翻译： 形成在DRAM的电容元件的下部电极上形成的电介质膜的氧气氛中的氧气的缺点是氧气渗透下部电极氧化阻挡层以形成高电阻和低介电常数的氧化物层。 在形成在信息容纳电容元件C的下部电极下方的通孔中的插塞表面上形成Ru Ru硅化物层，并且在Ru硅化物层的表面上进一步形成Ru氮化硅层。 在下电极上形成电介质膜的步骤中进行的氧气氛中进行高温热处理时，将Ru氮化硅层牺牲性氧化为Ru氮氧化硅，以防止Ru化硅化物层的氧化进行。

公开(公告)号：US06713343B2

公开(公告)日：2004-03-30

申请号：US10388618

申请日：2003-03-17

申请人： Yasuhiro Sugawara ,  Shinpei Iijima ,  Yuzuru Oji ,  Naruhiko Nakanishi ,  Misuzu Kanai ,  Masahiko Hiratani

发明人： Yasuhiro Sugawara ,  Shinpei Iijima ,  Yuzuru Oji ,  Naruhiko Nakanishi ,  Misuzu Kanai ,  Masahiko Hiratani

IPC分类号： H01L218242

CPC分类号： H01L27/1085 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/31604 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L28/40

摘要： An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.

摘要翻译： 集成半导体器件具有改进的可靠性并且适于更高的集成度，而不减少每个信息存储电容元件的累积电荷。 半导体器件具有DRAM，其具有存储单元，每个DRAM包括与形成在半导体衬底1的主表面上的存储单元选择MISFET Qs串联连接的信息存储电容元件C，具有下电极54，电容绝缘 膜58和上电极59.下电极54由在特定平面轴承（例如（002））面取向的钌膜制成，并且电容绝缘膜58由通过热处理得到的多晶钽膜制成 含有沉淀状态的结晶用氧化钽晶体的无定形氧化钽膜。

公开(公告)号：US20040011279A1

公开(公告)日：2004-01-22

申请号：US10325842

申请日：2002-12-23

申请人： Hynix Semiconductor Inc.

发明人： Kwang Chul Joo

IPC分类号： C30B023/00 ,  C30B025/00 ,  C30B028/12 ,  C30B028/14 ,  H01L021/8242 ,  H01L021/302 ,  H01L021/461

CPC分类号： H01L21/31604 ,  H01L21/02183 ,  H01L21/02205 ,  H01L21/02271 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/3144 ,  H01L21/31637 ,  H01L21/3211 ,  H01L28/40 ,  H01L29/40114

摘要： The present invention relates to a method of manufacturing a semiconductor device. The method includes forming a first doped polysilicon layer being a lower electrode on a semiconductor substrate, forming a Ta2O5 dielectric film using a carbon-free precursor and reaction gases, and forming an upper electrode on the dielectric film. As such, the Ta2O5 dielectric film is formed using a carbon-free precursor. The level of the leakage current is reduce, the insulating breakdown voltage is increased and reliability of the device is improved, particularly if the Ta2O5 dielectric thin film is used as an inter-poly dielectric material.

摘要翻译： 本发明涉及半导体器件的制造方法。 该方法包括：在半导体衬底上形成第一掺杂多晶硅层，其为下电极，使用无碳前体和反应气体形成Ta2O5电介质膜，并在电介质膜上形成上电极。 因此，使用无碳前体形成Ta 2 O 5介电膜。 泄漏电流的电平降低，绝缘击穿电压增加，器件的可靠性提高，特别是如果使用Ta2O5电介质薄膜作为多晶硅介电材料。

公开(公告)号：US06656788B2

公开(公告)日：2003-12-02

申请号：US09751843

申请日：2001-01-02

申请人： Dong Su Park ,  Byoung Kwon Ahn

发明人： Dong Su Park ,  Byoung Kwon Ahn

IPC分类号： H01L218242

CPC分类号： H01L21/02183 ,  C23C16/308 ,  H01L21/0228 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/31604 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/91

摘要： A capacitor for a semiconductor device is manufactured by forming a lower structure on a semiconductor device, forming a lower electrode on the lower structure of the semiconductor device, forming a dielectric thin film by depositing an amorphous TaON film on the surface of the lower electrode, and supplying a Ta source gas in a mono-pulse manner and continuously supplying a reaction gas even when the Ta source gas is not supplied, and forming an upper electrode on the upper portion of the dielectric thin film.

摘要翻译： 通过在半导体器件上形成下部结构，在半导体器件的下部结构上形成下部电极，通过在下部电极的表面上沉积非晶形的TaON膜来形成电介质薄膜，制造半导体器件的电容器， 并且即使在不供给Ta源气体的情况下也以单脉冲方式供给Ta源气体并连续地供给反应气体，并且在电介质薄膜的上部形成上电极。

公开(公告)号：US20030166346A1

公开(公告)日：2003-09-04

申请号：US10387091

申请日：2003-03-12

发明人： Ki-Yeon Park ,  Heung-Soo Park ,  Young-Wook Park

IPC分类号： H01L021/8242 ,  H01L021/31 ,  H01L021/469

CPC分类号： H01L21/02356 ,  C23C16/405 ,  C23C16/46 ,  C23C16/56 ,  H01L21/02183 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/31604 ,  H01L21/31691

摘要： Methods of forming Ta2O5 layers in a process chamber are disclosed. A Ta2O5 layer can be maintained at a first temperature that is less than a temperature for crystallization of the Ta2O5 layer. At least one of a position of the Ta2O5 layer in the process chamber relative to the heater and a pressure in the process chamber is changed to increase the temperature of the Ta2O5 layer to about the temperature for crystallization.

摘要翻译： 公开了在处理室中形成Ta 2 O 5层的方法。 可以将Ta 2 O 5层保持在小于Ta 2 O 5层的结晶温度的第一温度。 改变处理室中的Ta 2 O 5层相对于加热器的位置和处理室中的压力中的至少一个，以使Ta 2 O 5层的温度升高至约结晶温度。

公开(公告)号：US20030107073A1

公开(公告)日：2003-06-12

申请号：US10321614

申请日：2002-12-18

申请人： Hitachi, Ltd.

发明人： Shinpei Iijima ,  Yuzuru Ohji ,  Masato Kunitomo ,  Masahiko Hiratani ,  Yuichi Matsui ,  Hiroyuki Ohta ,  Yukihiro Kumagai

IPC分类号： H01L031/119 ,  H01L029/76 ,  H01L027/108 ,  H01L029/94

CPC分类号： H01L21/02183 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/31637 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/91

摘要： A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.