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公开(公告)号：US5175515A
公开(公告)日：1992-12-29
申请号：US719119
申请日：1991-06-21
Applicant: Michael G. Abernathy , Angie M. Fletcher , Paul Santeler , Roy E. Thomas, III
Inventor： Michael G. Abernathy , Angie M. Fletcher , Paul Santeler , Roy E. Thomas, III
CPC classification number: H05K1/0216 , H05K1/0237 , H05K2201/09254 , H05K2201/10689 , Y10T307/492
Abstract: An electrical system wherein the electrical conductive traces on the circuit boards are routed to achieve a balanced net to reduce noise caused by transmission line reflections. A trace is routed from the source terminal of the net to a balanced junction wherein if there are an odd number of load terminals, or loads, the balanced junction is located at one of the loads. The remaining loads are grouped into branches wherein each branch includes an equal number of loads. A trace is routed between each of the loads of each branch to serially connect the loads of each branch together, or, a trace is routed from a center one of the branch loads to each of the remaining branch loads, forming subbranches. In an alternate embodiment, a balanced subbranch is developed. The balanced load is connected to a pseudo-balanced load, which further receives an equal number of branches. The pseudo-balanced load is then connected to another pseudo-balanced load, which may also receive an equal number of branches. This pseudo-balanced load is connected to the source. In another alternative, two balanced subbranches have their balanced loads connected to a central balanced load. This balanced load may receive even further numbers of equal branches. The balanced load is connected to the source.
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公开(公告)号：US4777718A
公开(公告)日：1988-10-18
申请号：US880613
申请日：1986-06-30
Applicant: James M. Henderson , Ronald F. Kielmeyer, Jr.
Inventor： James M. Henderson , Ronald F. Kielmeyer, Jr.
CPC classification number: H05K1/167 , H01C17/07 , H01Q21/0075 , H05K2201/0355 , H05K2201/09254 , H05K2201/09536 , H05K2203/0361 , H05K3/06 , H05K3/427 , H05K3/4652 , Y10T29/49099 , Y10T29/49126 , Y10T29/49165
Abstract: A resistive element is formed on a printed circuit board using only printed circuit board fabrication techniques. A substrate having a bi-metallic cladding on one side of the substrate and a conductive metallic cladding on an opposing side of the substrate is used. A predetermined trace pattern is formed in the metallic cladding. Resistive elements are formed in the bi-metallic cladding opposing their desired locations in the trace pattern. The bi-metallic cladding consists of a resistive layer between the substrate and a second conductive layer. Tabs are etched in the second conductive layer, then resistors, which couple various tabs together, are etched in the resistive layer. Plated holes connect the tabs to desired locations in the trace pattern located on the opposing side of the substrate.
Abstract translation: 电阻元件仅使用印刷电路板制造技术形成在印刷电路板上。 使用在基板的一侧具有双金属包层的基板和在基板的相对侧上的导电金属包层。 在金属包层中形成预定的迹线图案。 电阻元件形成在双金属包层中，与其在迹线图案中的期望位置相对。 双金属包层由衬底和第二导电层之间的电阻层组成。 在第二导电层中蚀刻标签，然后在电阻层中蚀刻将各种接片连接在一起的电阻器。 电镀的孔将接片连接到位于衬底的相对侧上的迹线图案中的所需位置。
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公开(公告)号：US20240314925A1
公开(公告)日：2024-09-19
申请号：US18676296
申请日：2024-05-28
Applicant: L3 TECHNOLOGIES, INC.
Inventor： Brian Christopher Clark , Kris Allen Skowronski
CPC classification number: H05K1/025 , H01P3/08 , H05K2201/09236 , H05K2201/09254
Abstract: Power dividers (or splitters) and power combiners may be implemented using distributed lossy transmission lines that dissipate radio frequency (RF) and other electromagnetic (EM) signal energy. By taking advantage of natural PCB board loss at high operating frequencies, N-way power dividers with matched outputs and good isolation may be implemented without the use of discrete resistors. In one embodiment, a N-way power divider may be at least partially implemented on buried printed circuit board (PCB) layers (e.g., partially embedded) and, in a further embodiment a N-way may be implemented in a manner that is completely internal to the PCB (e.g., completely embedded), without the use of discrete resistors.
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公开(公告)号：US20240276641A1
公开(公告)日：2024-08-15
申请号：US18435062
申请日：2024-02-07
Inventor： Sheng-Ta WU , Li Jin DENG , Long CHANG , Lei QIU
IPC: H05K1/11 , H01L23/544 , H01L25/075
CPC classification number: H05K1/111 , H01L23/544 , H01L25/0753 , H01L2223/54426 , H05K2201/09254 , H05K2201/10106
Abstract: An electrical module is provided. The electrical module includes a circuit board. The circuit board includes at least one bonding pad. The bonding pad includes a bonding line and a plurality of traces. The traces are connected to the bonding line. The traces are configured in a radial manner. The bonding line includes a first section and a second section. The first section is connected to the second section. The first section extends in a first direction. The second section extends in a second direction. The first direction is perpendicular to the second direction. An extending direction of at least one of the traces differs from the first direction and the second direction.
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75.发明申请公开(公告)号：US20180279488A1
公开(公告)日：2018-09-27
申请号：US15991294
申请日：2018-05-29
Applicant: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
Inventor： Yutaro KOGAWA , Mitsunori SATO , Yutaka TAKEZAWA , Akitoshi SAKAUE , Mitsutoshi NAITO
CPC classification number: H05K3/4644 , G06F3/044 , G06F2203/04103 , G06F2203/04111 , G06F2203/04112 , H05K1/095 , H05K1/115 , H05K3/125 , H05K3/1275 , H05K3/28 , H05K2201/0108 , H05K2201/09236 , H05K2201/09254 , H05K2201/0979 , H05K2203/013 , H05K2203/0534 , Y10T29/49155
Abstract: By flexographic printing or inkjet printing, insulating ink is applied on a wiring pattern in accordance with a predetermined printing pattern. The insulating ink is hardened, whereby an insulating layer is formed. A contact region of the wiring pattern that is used for electrical connection with a conductor other than the wiring pattern is not covered with the insulating layer. The printing pattern is delimited by the outline of a non-printing region including the contact region. The wiring pattern includes, in the non-printing region, a trunk wiring line leading, to the contact region, from a position on the wiring pattern at which the wiring pattern overlaps with the outline and a branch wiring line extending from a point on at least one side of the trunk wiring line and terminating without making contact with the outline.
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Patent Agency Ranking
公开(公告)号：US20180259166A1
公开(公告)日：2018-09-13
申请号：US15779455
申请日：2016-11-22
Applicant: LG INNOTEK CO., LTD.
Inventor： Byeong Guk MIN
CPC classification number: F21V19/002 , F21K9/00 , F21K9/20 , F21S2/00 , F21V23/06 , F21Y2103/10 , F21Y2113/13 , F21Y2115/10 , H01L25/13 , H01L33/486 , H01L33/507 , H01L33/54 , H01L33/62 , H05K1/181 , H05K2201/09236 , H05K2201/09254 , H05K2201/10106 , H05K2201/10522
Abstract: An embodiment discloses a light source module. The disclosed light source module includes: a circuit board; and a plurality of light emitting diodes arranged on the circuit board, wherein the plurality of light emitting diodes include a plurality of first light emitting diodes connected to a power input terminal, and a plurality of second light emitting diodes connected to output ends of the plurality of first light emitting diodes, wherein the plurality of first light emitting diodes are spaced apart from each other, and at least two of the plurality of second light emitting diodes are disposed between the first light emitting diodes, respectively.
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公开(公告)号：US10064293B2
公开(公告)日：2018-08-28
申请号：US15363421
申请日：2016-11-29
Applicant: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
Inventor： Yutaro Kogawa , Mitsunori Sato , Yutaka Takezawa , Akitoshi Sakaue , Mitsutoshi Naito
CPC classification number: H05K3/4644 , G06F3/044 , G06F2203/04103 , G06F2203/04111 , G06F2203/04112 , H05K1/095 , H05K1/115 , H05K3/125 , H05K3/1275 , H05K3/28 , H05K2201/0108 , H05K2201/09236 , H05K2201/09254 , H05K2201/0979 , H05K2203/013 , H05K2203/0534 , Y10T29/49155
Abstract: By flexographic printing or inkjet printing, insulating ink is applied on a wiring pattern in accordance with a predetermined printing pattern. The insulating ink is hardened, whereby an insulating layer is formed. A contact region of the wiring pattern that is used for electrical connection with a conductor other than the wiring pattern is not covered with the insulating layer. The printing pattern is delimited by the outline of a non-printing region including the contact region. The wiring pattern includes, in the non-printing region, a trunk wiring line leading, to the contact region, from a position on the wiring pattern at which the wiring pattern overlaps with the outline and a branch wiring line extending from a point on at least one side of the trunk wiring line and terminating without making contact with the outline.
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公开(公告)号：US20180192509A1
公开(公告)日：2018-07-05
申请号：US15396181
申请日：2016-12-30
Applicant: Wil Choon Song , Khang Choong Yong , Min Suet Lim , Eng Huat Goh , Boon Ping Koh
Inventor： Wil Choon Song , Khang Choong Yong , Min Suet Lim , Eng Huat Goh , Boon Ping Koh
CPC classification number: H01P3/082 , H01P3/026 , H01P3/08 , H01P3/10 , H01P5/12 , H01P11/003 , H05K1/024 , H05K1/0242 , H05K1/0243 , H05K1/0245 , H05K2201/09254
Abstract: Various embodiments disclosed relate to a circuit. The circuit includes a transceiver adapted to generate a signal. A stranded transmission line is connected to the transceiver. The signal is then transmitted through the first pair of conductive strands.
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公开(公告)号：US09980366B2
公开(公告)日：2018-05-22
申请号：US14595175
申请日：2015-01-12
Applicant: QUALCOMM Incorporated
Inventor： Yokesh Subramanian
CPC classification number: H05K1/0213 , G11C5/025 , H05K1/0243 , H05K1/0246 , H05K1/0248 , H05K1/025 , H05K1/18 , H05K2201/09227 , H05K2201/09254
Abstract: An apparatus including an output driver on a PCB and a number of chips on the PCB, the chips including a first chip and a second chip. The PCB includes a first transmission line connected to the output driver, a second transmission line connected to the first transmission line and the first chip, the second transmission line having a length greater than or equal to 10 times a length of the first transmission line, and a third transmission line connected to the first transmission line and the second chip, the third transmission line having a length greater than or equal to 10 times the length of the first transmission line. The second transmission line connects to the first chip without being coupled to a termination resistor on the PCB and the third transmission line connects to the second chip without being coupled to a termination resistor on the PCB.
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公开(公告)号：US20180077790A1
公开(公告)日：2018-03-15
申请号：US15699202
申请日：2017-09-08
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yoichi Sawada
CPC classification number: H05K1/0228 , H03F1/26 , H03F3/195 , H03F3/213 , H03F3/245 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/451 , H03F2203/7209 , H04B1/40 , H05K1/165 , H05K1/181 , H05K2201/09254 , H05K2201/10015 , H05K2201/10053 , H05K2201/10098
Abstract: A high-frequency module includes: a power receiving terminal; an LNA, a reception switch that switches among a plurality of signals in different bands and outputs the signals to the LNA; a first conduction path spanning from the power receiving terminal to a power source terminal of the reception switch; a second conduction path spanning from a branching point in the first conduction path to a power source terminal of the LNA; a third conduction path branching from at least one of the first conduction path and the second conduction path and spanning to a ground; and a capacitor inserted into the third conduction path. A second inductance of the second conduction path is greater than a first inductance of a part spanning from the branching point in the first conduction path to the power source terminal.
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