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    Digital power gating with state retention
    81.
    发明授权
    Digital power gating with state retention 有权
    数字电源门控与状态保持

    公开(公告)号：US09007122B2

    公开(公告)日：2015-04-14

    申请号：US14202275

    申请日：2014-03-10

    Applicant: Via Technologies, Inc.

    Inventor： James R. Lundberg

    IPC: G05F1/10 ,  H03K17/22 ,  G06F1/32 ,  H03K19/00 ,  H03K17/16

    CPC classification number: H03K17/22 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/3296 ,  H03K17/16 ,  H03K19/0008 ,  H03K19/0016 ,  H03K2217/0036 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

    Abstract: A digital power gating system for performing power gating to reduce a voltage of a gated supply bus to a state retention voltage level that reduces leakage current while retaining a digital state of a functional circuit. The power gating system includes gating devices and a power gating control system. Each gating device has current terminals coupled between a global supply bus and the gated supply bus, and a control terminal controlled by a bit of a digital control value. The power gating control system successively adjusts the digital control value to reduce a voltage of the gated supply bus to the state retention voltage level. Adjustment gain and/or adjustment periods may be changed, such as when the digital control value reaches certain values or when the gated supply reaches certain voltage levels. Various parameters are programmable to adjust for particular configurations or to achieve desired operation.

    Abstract translation: 一种用于执行电力门控以将门控电源总线的电压降低到保持功能电路的数字状态的同时降低漏电流的状态保持电压电平的数字电源门控系统。 电源门控系统包括门控设备和电源门控控制系统。 每个选通装置具有耦合在全局电源总线和门控电源总线之间的电流端子，以及由位数位控制值控制的控制端子。 电源门控控制系统连续调整数字控制值，将门控电源总线的电压降至状态保持电压电平。 可以改变调节增益和/或调整周期，例如当数字控制值达到某些值时或当门控电源达到一定的电压电平时。 可以对各种参数进行编程以针对特定配置进行调整或实现​​期望的操作。

    MULTI-CORE SYNCHRONIZATION MECHANISM
    82.
    发明申请
    MULTI-CORE SYNCHRONIZATION MECHANISM 有权
    多核同步机制

    公开(公告)号：US20150067369A1

    公开(公告)日：2015-03-05

    申请号：US14281434

    申请日：2014-05-19

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Terry Parks

    IPC: G06F1/04 ,  G06F1/32

    CPC classification number: G06F1/3287 ,  G06F1/04 ,  G06F1/32 ,  G06F9/522 ,  G06F12/0891 ,  G06F2212/1028 ,  G06F2212/60

    Abstract: A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred.

    Abstract translation: 微处理器包括控制单元，该控制单元被配置为选择性地将各个时钟信号控制到多个处理核心中的每一个。 每个处理核心被配置为分别向控制单元写入一个值。 对于所述多个处理核心的每个核心，所述控制单元被配置为响应于所述核心向所述控制单元写入值而将相应的时钟信号关断到所述核心。 控制单元被配置为检测当所有处理核心已经向控制单元写入值并且控制单元已经将各个时钟信号截止到所有处理核心时发生的状况。 控制单元被配置为响应于检测到所发生的状况，同时将各个时钟信号接通到所有处理核心。

    METHOD FOR REDUCING POWER CONSUMPTION IN ELECTRONIC APPARATUS
    83.
    发明申请
    METHOD FOR REDUCING POWER CONSUMPTION IN ELECTRONIC APPARATUS 有权
    降低电子设备功耗的方法

    公开(公告)号：US20150067367A1

    公开(公告)日：2015-03-05

    申请号：US14057277

    申请日：2013-10-18

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Cheng-Ming HUANG

    IPC: G06F1/32

    CPC classification number: G06F1/324 ,  G06F1/3212 ,  Y02D10/126 ,  Y02D10/174

    Abstract: An electronic apparatus is provided. The electronic apparatus includes a serial advanced technology attachment (SATA) physical layer, a clock generator and a control unit. The SATA physical layer is configured to provide connection with an SATA device and perform data transmission with the SATA device is performed at a first clock frequency. The clock generator is configured to provide a clock signal having the first clock frequency to the SATA physical layer. When at least one specific event is detected by the control unit, the control unit controls the clock generator to provide the clock signal having a second clock frequency to the SATA physical layer, so that the SATA physical layer performs data transmission with the SATA device at the second clock frequency. The second clock frequency is lower than the first clock frequency.

    Abstract translation: 提供电子设备。 电子设备包括串行高级技术附件（SATA）物理层，时钟发生器和控制单元。 SATA物理层配置为提供与SATA设备的连接并执行数据传输，SATA设备以第一时钟频率执行。 时钟发生器被配置为向SATA物理层提供具有第一时钟频率的时钟信号。 当由控制单元检测到至少一个特定事件时，控制单元控制时钟发生器以向SATA物理层提供具有第二时钟频率的时钟信号，使得SATA物理层与SATA设备进行数据传输 第二个时钟频率。 第二个时钟频率低于第一个时钟频率。

    MICROPROCESSOR WITH BOOT INDICATOR THAT INDICATES A BOOT ISA OF THE MICROPROCESSOR AS EITHER THE X86 ISA OR THE ARM ISA
    86.
    发明申请
    MICROPROCESSOR WITH BOOT INDICATOR THAT INDICATES A BOOT ISA OF THE MICROPROCESSOR AS EITHER THE X86 ISA OR THE ARM ISA 有权
    具有引导指示器的微处理器显示了作为X86 ISA或ARM ISA的微处理器的引导ISA

    公开(公告)号：US20150067301A1

    公开(公告)日：2015-03-05

    申请号：US14526029

    申请日：2014-10-28

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. GLENN HENRY ,  TERRY PARKS ,  RODNEY E. HOOKER

    IPC: G06F15/82 ,  G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

    Abstract: A microprocessor includes a plurality of registers that holds an architectural state of the microprocessor and an indicator that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA. The microprocessor also includes a hardware instruction translator that translates x86 ISA instructions and ARM ISA instructions into microinstructions. The hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal. The microprocessor also includes an execution pipeline, coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. In response to the reset signal, the microprocessor initializes its architectural state in the plurality of registers as defined by the boot ISA prior to fetching the initial ISA instructions.

    Abstract translation: 微处理器包括保持微处理器架构状态的多个寄存器和指示微处理器的引导指令集体系结构（ISA）作为x86 ISA或高级RISC机器（ARM）ISA的指示符。 微处理器还包括硬件指令转换器，将x86 ISA指令和ARM ISA指令转换为微指令。 作为引导ISA的指令，硬件指令转换器将转换为接收复位信号后微处理器从架构存储器空间中提取的初始ISA指令。 微处理器还包括耦合到硬件指令转换器的执行流水线。 执行流水线执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。 响应于复位信号，微处理器在获取初始ISA指令之前初始化由引导ISA定义的多个寄存器中的架构状态。

    CORRECTABLE CONFIGURATION DATA COMPRESSION AND DECOMPRESSION SYSTEM
    89.
    发明申请
    CORRECTABLE CONFIGURATION DATA COMPRESSION AND DECOMPRESSION SYSTEM 有权
    正确的配置数据压缩和解密系统

    公开(公告)号：US20150058695A1

    公开(公告)日：2015-02-26

    申请号：US13972812

    申请日：2013-08-21

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Dinesh K. Jain

    IPC: H03M13/05 ,  G06F11/10

    CPC classification number: G06F11/10 ,  H03M7/702 ,  H03M13/05

    Abstract: An apparatus has a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die, the shared fuse array having a plurality of semiconductor fuses programmed with compressed configuration data and error checking and correction (ECC) codes. The plurality of microprocessor cores is disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores includes a reset controller that is configured to access the compressed configuration data and the ECC codes, to correct errors resulting in corrected compressed configuration data, to decompress all of the corrected compressed configuration data, and to distribute decompressed configuration data to initialize the elements.

    Abstract translation: 一种装置具有共享熔丝阵列和多个微处理器核心。 共享保险丝阵列设置在管芯上，共享保险丝阵列具有多个半导体保险丝，其编程有压缩配置数据和错误校验（ECC）代码。 多个微处理器核心设置在管芯上，其中多个微处理器核心中的每一个耦合到共享熔丝阵列，并且被配置为在上电/复位期间访问所有压缩的配置数据，用于初始化 多个核心中的每一个。 所述多个核心中的每一个包括复位控制器，其被配置为访问所述压缩配置数据和所述ECC代码，以校正导致校正的压缩配置数据的错误，以解压缩所有经校正的压缩配置数据，并且分发解压缩配置 数据初始化元素。

    APPARATUS AND METHOD FOR EXTENDED CACHE CORRECTION
    90.
    发明申请
    APPARATUS AND METHOD FOR EXTENDED CACHE CORRECTION 审中-公开
    扩展高速缓存校正的设备和方法

    公开(公告)号：US20150058564A1

    公开(公告)日：2015-02-26

    申请号：US13972481

    申请日：2013-08-21

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Dinesh K. Jain

    IPC: G06F12/08 ,  G06F3/06

    CPC classification number: G06F12/0802 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0673 ,  G06F11/1008 ,  G06F15/76 ,  G11C29/787 ,  G11C29/802

    Abstract: An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The a cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory.

    Abstract translation: 一种装置包括半导体熔丝阵列，高速缓冲存储器和多个核。 半导体熔丝阵列设置在芯片上，其中编程了配置数据。 半导体熔丝阵列具有第一多个半导体熔丝，其被配置为存储压缩的高速缓存校正数据。 高速缓冲存储器设置在管芯上。 多个芯设置在管芯上，其中多个芯中的每个芯耦合到半导体熔丝阵列和高速缓冲存储器，并且被配置为在上电/复位时访问半导体熔丝阵列，以解压缩压缩高速缓存 校正数据，并且分发解压缩的缓存校正数据以初始化高速缓冲存储器。

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