-
公开(公告)号：US09209216B2
公开(公告)日：2015-12-08
申请号：US13961429
申请日：2013-08-07
IPC分类号： H01L27/146
CPC分类号： H01L27/14692 , H01L27/1461 , H01L27/1462 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14636 , H01L27/1464 , H01L27/14645 , H01L27/14687
摘要： A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry.
摘要翻译： 用于形成背照式图像传感器的方法包括在晶体衬底上形成较高掺杂晶体层，在较高掺杂晶体层上生长较低掺杂晶体层，并从下部掺杂晶体层形成光电二极管和分量电路。 形成金属化结构以形成与组件之间的连接。 去除晶体衬底以暴露较高掺杂的晶体层。 在较高掺杂晶体层的暴露表面上提供光学部件结构以在其中接收光，使得较高掺杂晶体层为光电二极管和部件电路提供钝化层。
-
公开(公告)号：US09178042B2
公开(公告)日：2015-11-03
申请号：US13736534
申请日：2013-01-08
IPC分类号： H01L27/11 , H01L27/108 , H01L21/316 , H01L29/66 , H01L29/786 , H01L33/00
CPC分类号： H01L29/66742 , H01L29/66772 , H01L29/786 , H01L29/78654 , H01L29/78675 , H01L33/0041
摘要： A method for forming a thin film transistor includes joining a crystalline substrate to an insulating substrate. A doped layer is deposited on the crystalline substrate, and the doped layer is patterned to form source and drain regions. The crystalline substrate is patterned to form an active area such that a conductive channel is formed in the crystalline substrate between the source and drain regions. A gate stack is formed between the source and drain regions, and contacts are formed to the source and drain regions and the gate stack through a passivation layer.
摘要翻译： 一种形成薄膜晶体管的方法，包括将晶体衬底接合到绝缘衬底上。 掺杂层沉积在晶体衬底上，并且掺杂层被图案化以形成源区和漏区。 将晶体衬底图案化以形成有源区，使得在源区和漏区之间的晶体衬底中形成导电沟道。 在源极和漏极区域之间形成栅极堆叠，并且通过钝化层将触点形成到源极和漏极区域以及栅极堆叠。
-
公开(公告)号：US09166181B2
公开(公告)日：2015-10-20
申请号：US14184488
申请日：2014-02-19
CPC分类号： H01L51/0508 , H01L27/1222 , H01L27/1251 , H01L27/286 , H01L27/3244 , H01L27/326 , H01L27/3274 , H01L29/1066 , H01L29/267 , H01L29/66742 , H01L29/66916 , H01L29/808 , H01L51/002 , H01L51/0021 , H01L2227/323
摘要： Junction field-effect transistors including inorganic channels and organic gate junctions are used in some applications for forming high resolution active matrix displays. Arrays of such junction field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes.
摘要翻译： 包括无机通道和有机栅极结在内的结场场效应晶体管用于形成高分辨率有源矩阵显示器的一些应用中。 这种结型场效应晶体管的阵列电连接到薄膜开关晶体管，并为无源器件（例如有机发光二极管）提供高驱动电流。
-
公开(公告)号：US20150270326A1
公开(公告)日：2015-09-24
申请号：US14717344
申请日：2015-05-20
IPC分类号： H01L27/32 , H01L27/12 , H01L29/16 , H01L29/73 , H01L29/04 , H01L29/10 , H01L27/06 , H01L29/808
CPC分类号： H01L27/3276 , G09G3/3225 , G09G2300/0842 , H01L23/5226 , H01L27/0694 , H01L27/1207 , H01L27/3244 , H01L27/326 , H01L27/3265 , H01L29/04 , H01L29/1004 , H01L29/16 , H01L29/73 , H01L29/808 , H01L2251/5315 , H01L2251/533 , H01L2924/0002 , H01L2924/00
摘要： A hybrid integrated circuit device includes a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness. First devices are formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer. Second devices are formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side. A through via connection is configured to connect the first metallizations to the second metallizations through the dielectric layer. Pixel circuits and methods are also disclosed.
-
公开(公告)号：US20150235123A1
公开(公告)日：2015-08-20
申请号：US14684346
申请日：2015-04-11
CPC分类号： H01L51/0566 , G06N3/063 , G06N3/0635 , G11C11/54 , H01L21/28273 , H01L21/8238 , H01L29/0649 , H01L29/0665 , H01L29/0673 , H01L29/0843 , H01L29/0847 , H01L29/1029 , H01L29/1054 , H01L29/122 , H01L29/125 , H01L29/127 , H01L29/165 , H01L29/267 , H01L29/42324 , H01L29/432 , H01L29/51 , H01L29/66431 , H01L29/66462 , H01L29/66477 , H01L29/7783 , H01L29/7786 , H01L29/7788 , H01L29/7881 , H01L51/0055 , H01L51/0541 , H01L51/0545 , H01L51/0562 , H01L2251/301
摘要： Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
摘要翻译： 基于捕获和去除捕获空穴或电子和/或两种载体的复合的装置结构通过在接近界面深双极态或量子阱/点中的载流子捕获来获得，其用作半导体层中的双极阱，或者 在栅介质/阻挡层中。 在任一情况下，捕获的势垒很小，并且通过在深陷阱状态和/或量子阱/点中的载流子限制提供保留。 设备架构可用作三个终端或两个终端设备。
-
86.发明申请公开(公告)号：US20150230720A1
公开(公告)日：2015-08-20
申请号：US14185149
申请日：2014-02-20
IPC分类号： A61B5/04 , H01L21/8238 , H01L27/092 , H01L21/84 , H01L27/12
CPC分类号： H01L29/4175 , A61B5/04001 , A61B2562/028 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/16 , H01L29/785
摘要： High resolution active matrix nanowire circuits enable a flexible and stretchable platform for probing neural circuits. Fabrication of such circuits includes forming an array of transistors using a semiconductor-on-insulator substrate. Electrically isolated arrays of vertically extending, electrically conductive wires are formed from a doped, electrically conductive layer within the substrate, each of the arrays of wires being electrically connected to a transistor in the array of transistors.
摘要翻译： 高分辨率有源矩阵纳米线电路使得能够用于探测神经电路的灵活和可拉伸的平台。 这种电路的制造包括使用绝缘体上半导体衬底形成晶体管阵列。 垂直延伸的导电导线的电隔离阵列由衬底内的掺杂的导电层形成，每个导线阵列电连接到晶体管阵列中的晶体管。
-
公开(公告)号：US09105770B2
公开(公告)日：2015-08-11
申请号：US14055273
申请日：2013-10-16
IPC分类号： H01L21/00 , H01L31/0224 , H01L31/18
CPC分类号： H01L31/022466 , H01L31/02167 , H01L31/022441 , H01L31/0392 , H01L31/068 , H01L31/0682 , H01L31/18 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method for fabricating a photovoltaic device includes forming a first contact on a crystalline substrate, by epitaxially growing a first doped layer having a doping concentration of 1019 cm−3 or greater, a dislocation density of 105 cm−2 or smaller, a hydrogen content of 0.1 atomic percent or smaller, and a thickness configured to reduce Auger recombination in the epitaxially grown doped layer. A first passivation layer is formed on the first doped layer. A second contact is formed on the crystalline substrate on a side opposite the first contact by epitaxially growing a second doped layer having a doping concentration of 1019 cm−3 or greater, a dislocation density of 105 cm−2 or smaller, a hydrogen content of 0.1 atomic percent or smaller and a thickness configured to reduce Auger recombination in the second epitaxially grown doped layer. A second passivation layer is formed on the second doped layer.
-
公开(公告)号：US09059123B2
公开(公告)日：2015-06-16
申请号：US13949498
申请日：2013-07-24
IPC分类号： H01L27/32 , H01L23/522
CPC分类号： H01L27/3276 , G09G3/3225 , G09G2300/0842 , H01L23/5226 , H01L27/0694 , H01L27/1207 , H01L27/3244 , H01L27/326 , H01L27/3265 , H01L29/04 , H01L29/1004 , H01L29/16 , H01L29/73 , H01L29/808 , H01L2251/5315 , H01L2251/533 , H01L2924/0002 , H01L2924/00
摘要： A hybrid integrated circuit device includes a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness. First devices are formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer. Second devices are formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side. A through via connection is configured to connect the first metallizations to the second metallizations through the dielectric layer. Pixel circuits and methods are also disclosed.
摘要翻译： 混合集成电路器件包括绝缘体上半导体衬底，其具有基底衬底，半导体层和设置在其间的电介质层，所述基底衬底的厚度减小。 第一器件形成在半导体层中，第一器件在电介质层的第一侧连接到第一金属化层。 第二器件形成在基底衬底中，第二器件连接到形成在与第一侧相对的电介质层的第二侧上的第二金属化层。 通孔连接被配置为通过介电层将第一金属化连接到第二金属化。 还公开了像素电路和方法。
-
公开(公告)号：US09041079B1
公开(公告)日：2015-05-26
申请号：US14312467
申请日：2014-06-23
CPC分类号： G11C13/047 , G11C11/54 , G11C13/0014 , G11C13/0016 , G11C2213/53 , H01L27/1443 , H01L27/307 , H01L51/0071
摘要： An optoelectronic device may include an insulating substrate, a semiconductor channel region located on the insulating substrate, and a source region and a drain region in contact with the semiconductor channel region. A photoswitchable material may be located on the semiconductor channel region between the source region and the drain region, such that the photoswitchable material includes a first structural state based on being exposed to a first optical wavelength, and includes a second structural state based on being exposed to a second optical wavelength. The first structural state causes a first electrical current to flow between the source region and the drain region, while the second structural state causes a second electrical current to flow between the source region and the drain region.
摘要翻译： 光电子器件可以包括绝缘衬底，位于绝缘衬底上的半导体沟道区，以及与半导体沟道区接触的源区和漏区。 光可切换材料可以位于源极区域和漏极区域之间的半导体沟道区域上，使得可照光开关材料基于暴露于第一光学波长包括第一结构状态，并且包括基于暴露的第二结构状态 到第二光波长。 第一结构状态引起第一电流在源极区域和漏极区域之间流动，而第二结构状态引起第二电流在源极区域和漏极区域之间流动。
-
90.发明申请LATERAL HETEROJUNCTION BIPOLAR TRANSISTOR WITH LOW TEMPERATURE RECESSED CONTACTS 有权具有低温接触触点的侧向异相双极晶体管公开(公告)号：US20150093872A1
公开(公告)日：2015-04-02
申请号：US14042951
申请日：2013-10-01
IPC分类号： H01L29/66 , H01L21/306 , H01L21/283 , H01L29/267 , H01L21/02
CPC分类号： H01L29/66242 , H01L21/283 , H01L21/3086 , H01L29/0817 , H01L29/1004 , H01L29/7371
摘要： A method of forming the heterojunction bipolar transistor that includes providing a stack of a base layer, an extrinsic base layer, a first metal containing layer, and a dielectric cap layer. The dielectric cap layer and the first metal containing layer may be etched to provide a base contact and a dielectric cap. Exposed portions of the base layer may be etched selectively to the dielectric cap. A remaining portion of the base layer provides the base region. A hydrogenated silicon containing layer may be deposited with a low temperature deposition method. At least a portion of the hydrogenated silicon containing layer is formed on at least sidewalls of the base region. A second metal containing layer may be formed on the hydrogenated silicon containing layer. The second metal containing and the hydrogenated silicon containing layer may be etched to provide an emitter region and a collector region.
摘要翻译： 一种形成异质结双极晶体管的方法，其包括提供基底层，非本征基底层，第一金属含量层和电介质盖层的叠层。 可以蚀刻电介质盖层和第一含金属层以提供基极接触和电介质盖。 基底层的暴露部分可以选择性地蚀刻到电介质盖。 基层的剩余部分提供基区。 可以用低温沉积法沉积氢化含硅层。 氢化含硅层的至少一部分形成在基底区域的至少侧壁上。 可以在含氢硅层上形成第二含金属层。 可以蚀刻包含第二金属和含氢硅的层，以提供发射极区域和集电极区域。
-
-
-
-
-
-
-
-
-
搜索结果
594 条记录 (耗时 0.04 秒)
