公开(公告)号：US10211087B2

公开(公告)日：2019-02-19

申请号：US15812320

申请日：2017-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/764 ,  H01L21/306 ,  H01L21/02 ,  H01L21/027 ,  H01L21/266

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

公开(公告)号：US10090391B2

公开(公告)日：2018-10-02

申请号：US14864066

申请日：2015-09-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/812 ,  H01L27/12 ,  H01L29/51 ,  H01L29/49 ,  H01L29/47

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

公开(公告)号：US10038063B2

公开(公告)日：2018-07-31

申请号：US14300884

申请日：2014-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/812 ,  H01L27/12 ,  H01L29/51 ,  H01L29/49 ,  H01L29/47

CPC classification number: H01L29/41775 ,  H01L21/28052 ,  H01L27/1203 ,  H01L29/47 ,  H01L29/4933 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66848 ,  H01L29/66871 ,  H01L29/7835 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

公开(公告)号：US09947573B2

公开(公告)日：2018-04-17

申请号：US14476185

申请日：2014-09-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Natalie B. Feilchenfeld ,  Vibhor Jain ,  Qizhi Liu

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/08 ,  H01L29/66 ,  H01L29/868 ,  H01L29/872 ,  H01L29/165 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L21/76224 ,  H01L27/0814 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66136 ,  H01L29/868 ,  H01L29/872

Abstract: Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p- and n-terminals formed in an i-region above a substrate.

公开(公告)号：US09726547B2

公开(公告)日：2017-08-08

申请号：US14553203

申请日：2014-11-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qizhi Liu ,  Anthony K. Stamper ,  Ronald F. Waller

IPC: G01J5/20 ,  H01J37/317 ,  H01L37/00

CPC classification number: G01J5/20 ,  G01J5/024 ,  G01J2005/202 ,  G01J2005/206 ,  H01J37/3171 ,  H01J2237/31701 ,  H01L37/00

Abstract: A microbolometer device integrated with CMOS and BiCMOS technologies and methods of manufacture are disclosed. The method includes forming a microbolometer unit cell, comprises damaging a portion of a substrate to form a damaged region. The method further includes forming infrared (IR) absorbing material on the damaged region. The method further includes isolating the IR absorbing material by forming a cavity underneath the IR absorbing material.

公开(公告)号：US09653477B2

公开(公告)日：2017-05-16

申请号：US14147186

申请日：2014-01-03

Applicant: International Business Machines Corporation

Inventor： Peng Cheng ,  James S. Dunn ,  Blaine J. Gross ,  Qizhi Liu ,  James A. Slinkman

IPC: H01L21/336 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/165 ,  H01L29/45 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L27/1203 ,  H01L21/3081 ,  H01L21/764 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7842

Abstract: Various embodiments include field effect transistors (FETs) and methods of forming such FETs. One method includes: forming a first set of openings in a precursor structure having: a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer; and a sacrificial layer overlying the second oxide, wherein the first set of openings each expose the silicon substrate; undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a trench corresponding with each of the first set of openings; passivating exposed surfaces of at least one of the SiGe layer or the silicon layer in the first set of openings; and at least partially filling each trench with a dielectric.

公开(公告)号：US09564508B2

公开(公告)日：2017-02-07

申请号：US14528435

申请日：2014-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mattias E. Dahlstrom ,  Dinh Dang ,  Qizhi Liu ,  Ramana M. Malladi

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/763 ,  H01L23/367 ,  H01L29/08 ,  H01L29/737 ,  H01L21/306 ,  H01L21/308 ,  H01L23/373

CPC classification number: H01L29/66242 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/763 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L29/0821 ,  H01L29/7371 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core.

Abstract translation: 制造半导体结构的方法包括通过浅沟槽隔离（STI）结构形成沟槽并且形成衬底，以及在沟槽的侧壁上形成包括电绝缘体材料的衬垫。 该方法还包括在沟槽和衬垫上形成包括高导热性材料的芯，并在沟槽和芯上形成帽。

公开(公告)号：US09355972B2

公开(公告)日：2016-05-31

申请号：US14196137

申请日：2014-03-04

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Qizhi Liu

IPC: H01L23/66 ,  H01L49/02 ,  H01L29/06 ,  H01L23/522 ,  H01L21/762

CPC classification number: H01L23/5223 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

Abstract translation: 在混合信号集成电路（IC）的体硅（Si）衬底中制造电介质区域的结构和方法提供了高Q无源谐振器。 通过湿法蚀刻在<100>方向内的本体Si衬底内的深沟槽扩大以形成连续的空腔，其由Si氧化物填充以形成电介质区域。 电介质区域增强了在混合信号IC的金属化层中形成的覆盖无源谐振器的质量（Q）。

公开(公告)号：US09349793B2

公开(公告)日：2016-05-24

申请号：US14480215

申请日：2014-09-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L21/306 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/764 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76289 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0273 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

Abstract translation: 公开了具有下面的气隙的场效应晶体管（FET）和制造方法。 该方法包括在衬底的预定深度处形成非晶层。 该方法还包括在非晶层下方的衬底中形成气隙。 该方法还包括在非晶层和气隙之上的衬底的有源区中形成完全隔离的晶体管。

公开(公告)号：US09274277B2

公开(公告)日：2016-03-01

申请号：US14278689

申请日：2014-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brennan J. Brown ,  James R. Elliott ,  Qizhi Liu ,  Steven M. Shank

IPC: G02B6/12 ,  G02B6/125 ,  G02B6/132 ,  G02B6/136 ,  H01L31/0232 ,  H01L33/58

CPC classification number: G02B6/125 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B2006/12061 ,  H01L31/02327 ,  H01L33/58

Abstract: Si waveguide devices on a bulk Si substrate with supporting anchors and methods of manufacture are disclosed. The method includes forming a waveguide device over an Si substrate, and forming one or more anchors from the Si substrate. The one or more anchors support the waveguide device.

Abstract translation: 公开了具有支撑锚固体和制造方法的体积Si衬底上的Si波导器件。 该方法包括在Si衬底上形成波导器件，并从Si衬底形成一个或多个锚固件。 一个或多个锚固件支撑波导装置。