公开(公告)号：US20080224259A1

公开(公告)日：2008-09-18

申请号：US12106374

申请日：2008-04-21

申请人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L29/00 ,  H01L21/02

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

公开(公告)号：US20080185684A1

公开(公告)日：2008-08-07

申请号：US12098479

申请日：2008-04-07

申请人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L29/92

CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.

公开(公告)号：US07394145B2

公开(公告)日：2008-07-01

申请号：US11928798

申请日：2007-10-30

申请人： Anil K Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在所述电介质层中形成通过所述介电层与所述无源元件的互连以及与所述虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US20080045011A1

公开(公告)日：2008-02-21

申请号：US11506227

申请日：2006-08-18

申请人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

IPC分类号： H01L21/44

CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/28123

摘要： A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.

公开(公告)号：US07298935B1

公开(公告)日：2007-11-20

申请号：US11415923

申请日：2006-05-01

申请人： Charles T. Black ,  Gian-Luca Bona ,  Timothy J. Dalton ,  Nicholas C. M. Fuller ,  Roland Germann ,  Maurice McGlashan-Powell ,  Chandrasekhar Narayan ,  Robert L. Sandstrom

发明人： Charles T. Black ,  Gian-Luca Bona ,  Timothy J. Dalton ,  Nicholas C. M. Fuller ,  Roland Germann ,  Maurice McGlashan-Powell ,  Chandrasekhar Narayan ,  Robert L. Sandstrom

IPC分类号： G02B6/00

CPC分类号： G02B6/126 ,  B29D11/00759 ,  G02B6/136 ,  G02B2006/1215

摘要： A method in effectuating the redirection of light which is propagated within a waveguide, and which eliminates the necessity for a bending of the waveguide, or the drawbacks encountered in directional changes in propagated light involving the need for sharp curves of essentially small-sized radii, which would resultingly lead to excessive losses in light. In this connection, the method relates to the fabricating and the provision of a wire-grid polarization beam splitter within an optical waveguide, which utilizes a diblock copolymer template to formulate the wire-grid.

摘要翻译： 实现在波导内传播的光的重定向并且消除波导的弯曲的必要性的方法或者涉及需要基本上小的半径的尖锐曲线的传播光的方向性变化中遇到的缺点， 这将导致轻微的过度损失。 在这方面，该方法涉及在光波导内制造和提供线栅偏振分束器，其利用二嵌段共聚物模板来配制线栅。

公开(公告)号：US07253116B2

公开(公告)日：2007-08-07

申请号：US10904608

申请日：2004-11-18

申请人： Nicholas C. M. Fuller ,  Timothy J. Dalton

发明人： Nicholas C. M. Fuller ,  Timothy J. Dalton

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76802 ,  G03F7/427 ,  H01L21/31138

摘要： A high ion energy and high pressure O2/CO-based plasma for ashing field photoresist material subsequent to via-level damascene processing. The optimized plasma ashing process is performed at greater than approximately 300 mT pressure and ion energy greater than approximately 500 W conditions with an oxygen partial pressure of greater than approximately 85%. The rapid ash rate of the high pressure/high ion energy process and minimal dissociation conditions (no “source” power is applied) allow minimal interaction between the interlevel dielectric and ash chemistry to achieve minimal overall sidewall modification of less than approximately 5 nm.

摘要翻译： 用于经过层级镶嵌处理之后灰化场致光材料的高离子能量和高压O 2 2 / CO基等离子体。 优化的等离子体灰化过程在大于约300mT的压力下进行，离子能量大于约500W条件，氧分压大于约85％。 高压/高离子能量过程的快速灰分速率和最小解离条件（不施加“源”功率）允许层间电介质和灰分化学之间的最小相互作用，以实现小于约5nm的最小总体侧壁修饰。

公开(公告)号：US07064064B2

公开(公告)日：2006-06-20

申请号：US11058783

申请日：2005-02-16

申请人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

摘要翻译： 公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。 互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

公开(公告)号：US06933191B2

公开(公告)日：2005-08-23

申请号：US10605260

申请日：2003-09-18

申请人： Glenn A. Biery ,  Zheng G. Chen ,  Timothy J. Dalton ,  Naftali E. Lustig

发明人： Glenn A. Biery ,  Zheng G. Chen ,  Timothy J. Dalton ,  Naftali E. Lustig

IPC分类号： H01L21/02 ,  H01L21/027 ,  H01L21/20 ,  H01L21/8242

CPC分类号： H01L28/20 ,  H01L21/0274 ,  H01L28/40

摘要： MIM capacitors and thin film resistors are fabricated with at least one less lithographic step than the prior art methods. The process step reduction is realized by using semi-transparent metallic electrodes, fabricated with a two-mask process, which provides for direct alignment, and eliminates the need for alignment trenches in an additional layer.

摘要翻译： MIM电容器和薄膜电阻器与现有技术的方法相比制造的光刻步骤至少少一个。 通过使用通过双掩模工艺制造的半透明金属电极实现工艺步骤减少，其提供直接对准，并且不需要在附加层中对准沟槽。

公开(公告)号：US06831363B2

公开(公告)日：2004-12-14

申请号：US10319032

申请日：2002-12-12

申请人： Timothy J. Dalton ,  Sanjit K. Das ,  Brett H. Engel ,  Brian W. Herbst ,  Habib Hichri ,  Bernd E. Kastenmeier ,  Kelly Malone ,  Jeffrey R. Marino ,  Arthur Martin ,  Vincent J. McGahay ,  Ian D. Melville ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant

发明人： Timothy J. Dalton ,  Sanjit K. Das ,  Brett H. Engel ,  Brian W. Herbst ,  Habib Hichri ,  Bernd E. Kastenmeier ,  Kelly Malone ,  Jeffrey R. Marino ,  Arthur Martin ,  Vincent J. McGahay ,  Ian D. Melville ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant

IPC分类号： H01L2348

CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.

摘要翻译： 用于半导体器件的互连结构包括在较低金属化水平上形成的有机低介电常数（低k）电介质层。 形成的通孔在低k电介质层内，通孔连接在下金属化层形成的下金属化线与上金属化层形成的上金属化线。 通孔被选自具有热膨胀系数（CTE）的材料的结构轴环包围，以便在低k电介质层的热膨胀之后保护通孔不受剪切力的影响。

公开(公告)号：US06815813B1

公开(公告)日：2004-11-09

申请号：US10604211

申请日：2003-07-01

申请人： Timothy J. Dalton ,  Kevin S. Petrarca ,  Michelle L. Steen ,  Cornelia K. Tsang ,  Richard P. Volant

发明人： Timothy J. Dalton ,  Kevin S. Petrarca ,  Michelle L. Steen ,  Cornelia K. Tsang ,  Richard P. Volant

IPC分类号： H01L2334

CPC分类号： H01L23/58 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method are provided for thermal dissipation from a heat producing electronic device. The system includes a substrate for fabricating integrated circuits, the substrate having a first face and a second face. The second face is disposed substantially parallel to the first face having an electronic device disposed therein. A metallized crack stop is disposed in the first face surrounding the electronic device. A plurality of first metal conduits extend through the substrate from the second face thereof to the crack stop, wherein each first metal conduit is in thermal contact with the crack stop to provide a thermal drain from the electronic device to the second face.

摘要翻译： 提供了一种从制热电子设备散热的系统和方法。 该系统包括用于制造集成电路的基板，该基板具有第一面和第二面。 第二面基本上平行于第一面设置，其中设置有电子装置。 在电子设备周围的第一面设有金属化的裂纹停止件。 多个第一金属导管从其第二面延伸穿过基板到裂缝停止部，其中每个第一金属导管与裂纹停止件热接触以提供从电子装置到第二面的热耗散。