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    Semiconductor package assembly with through silicon via interconnect
    82.
    发明授权
    Semiconductor package assembly with through silicon via interconnect 有权
    半导体封装组件通过硅芯片通过互连

    公开(公告)号：US09570399B2

    公开(公告)日：2017-02-14

    申请号：US14963451

    申请日：2015-12-09

    Applicant: MediaTek Inc.

    Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Wei-Che Huang ,  Yu-Hua Huang ,  Tzu-Hung Lin ,  Kuei-Ti Chan ,  Ruey-Beei Wu ,  Kai-Bin Wu

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00

    CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06541 ,  H01L2225/06544

    Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. A first ground TSV interconnect is disposed within the interval region. A second semiconductor die is mounted on the first semiconductor die, having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.

    Abstract translation: 本发明提供一种具有TSV互连的半导体封装组件。 半导体封装组件包括安装在基座上的第一半导体管芯。 第一半导体管芯包括半导体衬底。 通过半导体衬底形成TSV互连的第一阵列和TSV互连的第二阵列，其中TSV互连的第一阵列和第二阵列被间隔区隔开。 第一接地TSV互连设置在间隔区域内。 第二半导体管芯安装在第一半导体管芯上，其上具有接地焊盘。 第一半导体管芯的第一接地TSV互连具有耦合到第二半导体管芯的接地焊盘的第一端子和耦合到布置在半导体衬底的前侧上的互连结构的第二端子。

    Semiconductor package structure having an annular frame with truncated corners
    87.
    发明授权
    Semiconductor package structure having an annular frame with truncated corners 有权

    公开(公告)号：US12142598B2

    公开(公告)日：2024-11-12

    申请号：US18170078

    申请日：2023-02-16

    Applicant: MEDIATEK INC.

    Inventor： Chia-Cheng Chang ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Yi-Jou Lin

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538

    Abstract: A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.

    CHIP SCALE PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
    90.
    发明申请
    CHIP SCALE PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20220392839A1

    公开(公告)日：2022-12-08

    申请号：US17886704

    申请日：2022-08-12

    Applicant: MediaTek Inc.

    Inventor： Yen-Yao Chi ,  Nai-Wei Liu ,  Ta-Jen Yu ,  Tzu-Hung Lin ,  Wen-Sung Hsu

    IPC: H01L23/528 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00

    Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.

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