公开(公告)号：US20150042378A1

公开(公告)日：2015-02-12

申请号：US14523923

申请日：2014-10-26

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K19/0175 ,  G11C11/401 ,  H03K19/00

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: In a memory module having an integrated-circuit buffer device coupled to one or more integrated-circuit memory devices, the buffer device receives write data signals from an external control component via a set of data inputs, the write data signals indicating write data to be stored within one or more of the memory devices. Logic within the buffer device sequentially applies controllable termination impedance configurations at the data inputs based on an indication received from the control component and an internal state of the buffer device, applying a first controllable termination impedance configuration at each of the data inputs during a first internal state of the buffer device corresponding to the reception of the write data signals on the data inputs, and applying a second controllable termination impedance configuration at each of the data inputs during a second internal state of the buffer device that succeeds the first internal state.

Abstract translation: 在具有耦合到一个或多个集成电路存储器件的集成电路缓冲器件的存储器模块中，缓冲器件经由一组数据输入从外部控制部件接收写入数据信号，写入数据信号指示写入数据为 存储在一个或多个存储器件中。 缓冲装置内的逻辑基于从控制部件接收到的指示和缓冲装置的内部状态，顺序地在数据输入端施加可控终端阻抗配置，在第一内部的每个数据输入端施加第一可控终端阻抗配置 所述缓冲器装置的状态与所述数据输入上的所述写数据信号的接收相对应，以及在所述第一内部状态的所述缓冲器件的第二内部状态期间，在每个所述数据输入端施加第二可控终端阻抗配置。

公开(公告)号：US20140173240A1

公开(公告)日：2014-06-19

申请号：US14153822

申请日：2014-01-13

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G06F13/16 ,  G11C7/10

CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

Abstract translation: 具有时间交错请求信号输出的存储器控​​制器。 产生第一定时信号，同时产生具有相对于第一定时信号的第一相位差的第二定时信号。 响应于第一定时信号发送地址值，响应于构成第一存储器访问请求的第二定时信号，地址值和控制值发送控制值。

公开(公告)号：US20140164823A1

公开(公告)日：2014-06-12

申请号：US14098322

申请日：2013-12-05

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Brent Haukness ,  Mehmet Günhan Ertosun ,  Ian P. Shaeffer

IPC: G06F11/20

CPC classification number: G06F11/2053 ,  G11C13/0002 ,  G11C13/0033 ,  G11C16/3431 ,  G11C29/50008 ,  G11C29/52 ,  G11C2029/0409

Abstract: Components of a memory system, such as a memory controller and memory device, which detect accumulated memory read disturbances and correct such disturbances before they reach a level that causes errors. The memory device includes a memory array and a disturbance control circuit. The memory array includes a plurality of memory rows. Each memory row is associated with a disturbance warning circuit having a state that corresponds to an accumulated disturbance in the memory row. The disturbance control circuit determines, responsive to an activation of a memory row of the plurality of memory rows specified by a row access command, whether the disturbance condition is present in the memory row based on the state of the disturbance warning circuit associated with the memory row. If a disturbance condition is present, the disturbance control circuit causes a recovery operation to be performed on the memory row to reduce the accumulated disturbances.

Abstract translation: 诸如存储器控制器和存储器件的存储器系统的组件，其在累积的存储器读出干扰之前检测累积的存储器读取干扰并且在达到导致错误的电平之前校正这种干扰。 存储器件包括存储器阵列和干扰控制电路。 存储器阵列包括多个存储器行。 每个存储器行与具有对应于存储器行中的累积干扰的状态的干扰警告电路相关联。 干扰控制电路响应于由行访问命令指定的多个存储行的存储器行的激活，基于与存储器相关联的干扰警告电路的状态来确定存储器行中是否存在干扰条件 行。 如果存在干扰条件，则扰动控制电路使得对存储器行进行恢复操作以减少累积的干扰。

公开(公告)号：US12189548B2

公开(公告)日：2025-01-07

申请号：US17534180

申请日：2021-11-23

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F13/16 ,  G06F1/3234 ,  G06F12/02 ,  G06F13/40

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

公开(公告)号：US12066958B2

公开(公告)日：2024-08-20

申请号：US18135095

申请日：2023-04-14

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F13/16 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G11C7/22 ,  G11C7/04 ,  H04L7/033

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/222 ,  G11C7/04 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US11349478B2

公开(公告)日：2022-05-31

申请号：US16940349

申请日：2020-07-27

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K19/00 ,  G06F13/40 ,  G11C11/4093 ,  H03K19/0175 ,  G11C11/401 ,  G11C11/419 ,  G11C16/26 ,  G11C11/41 ,  G11C11/4063 ,  G11C11/413 ,  G11C11/417 ,  G11C16/06 ,  G11C16/32 ,  G06F3/06

Abstract: In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.

公开(公告)号：US20220084571A1

公开(公告)日：2022-03-17

申请号：US17305654

申请日：2021-07-12

Applicant: Rambus Inc.

Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

IPC: G11C7/22 ,  G06F13/16 ,  G11C7/02

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

公开(公告)号：US11062748B2

公开(公告)日：2021-07-13

申请号：US16459330

申请日：2019-07-01

Applicant: Rambus Inc.

Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

IPC: G11C7/22 ,  G06F13/16 ,  G11C7/02

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

公开(公告)号：US20210193197A1

公开(公告)日：2021-06-24

申请号：US16953207

申请日：2020-11-19

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C7/10 ,  G06F13/16 ,  G06F12/00

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US20210098280A1

公开(公告)日：2021-04-01

申请号：US17068717

申请日：2020-10-12

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Ian P. Shaeffer

IPC: H01L21/768 ,  H01L25/065

Abstract: This application is directed to a system including a plurality of devices that are stacked one on top of another. Each device includes a substrate having two opposing surfaces. A first row of contacts is coupled on a first surface and includes a first contact and a second contact that are adjacent to each other. A second row of contacts is coupled on a respective second surface and includes a third contact. Each contact in the second row of contacts is physically aligned with an opposite contact in the first row. The third contact is disposed opposite and physically aligned with the first contact in the first row, and electrically coupled to the second contact in the first row. Operational circuitry is electrically coupled to at least the first contact on the first row, and at least two of the plurality of devices have distinct operational circuitry.