公开(公告)号：US09659945B2

公开(公告)日：2017-05-23

申请号：US14837177

申请日：2015-08-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L21/8239 ,  H01L21/8242 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/12 ,  H01L49/02 ,  H01L27/108 ,  H01L29/786 ,  H01L23/528 ,  H01L29/24 ,  H01L29/78 ,  G11C16/04 ,  H01L21/285 ,  H01L29/66

Abstract: A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

公开(公告)号：US09484467B2

公开(公告)日：2016-11-01

申请号：US14930081

申请日：2015-11-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Masakazu Murakami

IPC: H01L21/34 ,  H01L29/24 ,  H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/45

Abstract: A semiconductor device with significantly low off-state current is provided. An oxide semiconductor material in which holes have a larger effective mass than electrons is used. A transistor is provided which includes a gate electrode layer, a gate insulating layer, an oxide semiconductor layer including a hole whose effective mass is 5 or more times, preferably 10 or more times, further preferably 20 or more times that of an electron in the oxide semiconductor layer, a source electrode layer in contact with the oxide semiconductor layer, and a drain electrode layer in contact with the oxide semiconductor layer.

公开(公告)号：US09477294B2

公开(公告)日：2016-10-25

申请号：US14055200

申请日：2013-10-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuji Nishijima ,  Hidetomo Kobayashi ,  Tomoaki Atsumi ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

Abstract: A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register in the peripheral circuit is provided in an interface with a bus line. A power gate for controlling supply control is provided. The microcontroller can operate not only in a normal operation mode where all circuits are active, but also in a low power consumption mode where some of the circuits are active. A volatile memory and nonvolatile memory are provided in a register, such as a register of the CPU. Data in the volatile memory is backed up in the nonvolatile memory before the power supply is stopped. In the case where the operation mode returns to the normal mode, when power supply is started again, data in the nonvolatile memory is written back into the volatile memory.

Abstract translation: 提供以低功耗模式工作的微控制器。 微控制器包括CPU，存储器和诸如定时器电路的外围电路。 外围电路中的寄存器设置在与总线线路的接口中。 提供用于控制电源控制的电源门。 微控制器不仅可以在所有电路都有效的正常工作模式下工作，而且还可以在一些电路处于活动状态的低功耗模式下工作。 在诸如CPU的寄存器的寄存器中提供易失性存储器和非易失性存储器。 在电源停止之前，易失性存储器中的数据被备份在非易失性存储器中。 在操作模式返回到正常模式的情况下，当再次开始供电时，非易失性存储器中的数据被写回到易失性存储器中。

公开(公告)号：US09454923B2

公开(公告)日：2016-09-27

申请号：US14277248

申请日：2014-05-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hidetomo Kobayashi ,  Kiyoshi Kato ,  Wataru Uesugi

IPC: H03K17/687 ,  G09G3/00 ,  H03K19/00 ,  H01L27/06 ,  H01L27/12 ,  H01L29/78

CPC classification number: G09G3/00 ,  G09G2330/022 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/7833 ,  H03K19/0016

Abstract: A semiconductor device with short overhead time. The semiconductor device includes a first wiring supplied with a power supply potential, a second wiring, a switch for controlling electrical connection between the first wiring and the second wiring, a load electrically connected to the second wiring, a transistor whose source and drain are electrically connected to the second wiring, and a power management unit having functions of controlling the conduction state of the switch and controlling a gate potential of the transistor. A channel formation region of the transistor is included in an oxide semiconductor film.

Abstract translation: 具有短占空时间的半导体器件。 所述半导体器件包括供给电源电位的第一布线，第二布线，用于控制所述第一布线和所述第二布线之间的电连接的开关，电连接到所述第二布线的负载，源极和漏极电连接的晶体管 连接到第二布线，以及功率管理单元，具有控制开关的导通状态和控制晶体管的栅极电位的功能。 晶体管的沟道形成区域包括在氧化物半导体膜中。

公开(公告)号：US09425215B2

公开(公告)日：2016-08-23

申请号：US14801936

申请日：2015-07-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Jun Koyama ,  Yutaka Shionoiri

IPC: H01L27/14 ,  H01L27/12 ,  H01L23/66 ,  H01L23/538 ,  G06K19/07 ,  H01L27/13 ,  H01L29/786

CPC classification number: H01L27/1222 ,  G06K19/0723 ,  H01L23/5387 ,  H01L23/66 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/13 ,  H01L29/78621 ,  H01L29/78648 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.

公开(公告)号：US09153589B2

公开(公告)日：2015-10-06

申请号：US13900581

申请日：2013-05-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato ,  Shuhei Nagatsuka ,  Takanori Matsuzaki ,  Hiroki Inoue

IPC: H01L29/788 ,  H01L27/108 ,  H01L27/115 ,  G11C16/04 ,  H01L27/105 ,  H01L27/12 ,  H01L27/11 ,  H01L49/02

CPC classification number: H01L29/7869 ,  G11C16/0425 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/78693 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

Abstract translation: 半导体器件包括源极线，位线，信号线，字线，在源极线和位线之间并联连接的存储器单元，通过开关电连接到源极线和位线的第一驱动器电路 元件，通过开关元件电连接到源极线的第二驱动器电路，电连接到信号线的第三驱动电路，以及电连接到字线的第四驱动电路。 存储单元包括第一晶体管，包括第一栅电极，第一源电极和第一漏电极，第二晶体管包括第二栅电极，第二源电极和第二漏极，以及电容器。 第二晶体管包括氧化物半导体材料。

公开(公告)号：US09135958B2

公开(公告)日：2015-09-15

申请号：US14451671

申请日：2014-08-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: G11C5/06 ,  G11C16/04 ,  G11C16/28 ,  H01L21/02 ,  H01L27/06 ,  H01L27/105 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  G11C11/24 ,  H01L29/26 ,  H01L29/22 ,  G11C5/14 ,  G11C7/12 ,  H01L27/115 ,  G11C7/18 ,  G11C11/4097

CPC classification number: G11C7/10 ,  G11C5/06 ,  G11C5/147 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C11/24 ,  G11C11/4097 ,  G11C16/0433 ,  G11C16/28 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/22 ,  H01L29/24 ,  H01L29/26 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.

Abstract translation: 本发明的目的是提供一种半导体器件，其组合晶体管，其集成在其沟道形成区域中包括氧化物半导体的相同衬底晶体管和在其沟道形成区域中包括非氧化物半导体的晶体管。 本发明的应用是实现基本上不需要特定擦除操作的非易失性半导体存储器，并且不会因重复的写入操作而遭受损坏。 此外，半导体器件很适合于存储多值数据。 在说明书中详细说明制造方法，应用电路和驱动/读取方法。

公开(公告)号：US09130558B2

公开(公告)日：2015-09-08

申请号：US14219301

申请日：2014-03-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/00 ,  G06F1/32

CPC classification number: H03K19/0008 ,  G06F1/32 ,  H01L29/045 ,  H01L29/24 ,  H03K19/0013

Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.

Abstract translation: 为了降低功耗，具有基于输入信号进行逻辑运算处理的功能的运算电路，将根据逻辑运算处理结果存储的电位存储为存储数据，并输出具有值的信号 对应于存储的数据作为输出信号。 算术电路包括执行逻辑运算处理的运算部，控制是否设定了与逻辑运算处理结果对应的电位的第一电位的第一场效应晶体管，以及控制是否 输出信号数据的电位被设定为作为参考电位的第二电位。

公开(公告)号：US09087280B2

公开(公告)日：2015-07-21

申请号：US14266930

申请日：2014-05-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Jun Koyama ,  Yutaka Shionoiri

IPC: H01L27/14 ,  G06K19/07 ,  H01L27/12 ,  H01L27/13 ,  H01L29/786

CPC classification number: H01L27/1222 ,  G06K19/0723 ,  H01L23/5387 ,  H01L23/66 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/13 ,  H01L29/78621 ,  H01L29/78648 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.

Abstract translation: 本发明提供一种处理器，其通过在对热敏感的基板（例如塑料基板或塑料膜基板）上形成使用多晶半导体的高功能集成电路。 此外，本发明提供一种无线发送和接收电力或信号的无线处理器，无线存储器及其信息处理系统。 根据本发明，一种信息处理系统包括一个元件形成区域，该元件形成区域包括晶体管，该晶体管至少具有由半导体膜形成的沟道形成区域，所述半导体膜片分隔成10至200nm的厚度的岛状物以及天线。 晶体管固定在柔性基板上。 其中形成包括元件形成区域的高功能集成电路并且半导体器件通过天线发送和接收数据的无线处理器。

公开(公告)号：US09053969B2

公开(公告)日：2015-06-09

申请号：US13803256

申请日：2013-03-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L27/105 ,  H01L21/84 ,  H01L27/108 ,  H01L27/115 ,  H01L27/12 ,  H01L27/13 ,  G11C16/04

CPC classification number: H01L27/105 ,  G11C16/0425 ,  G11C16/0433 ,  H01L21/84 ,  H01L27/108 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/13

Abstract: The semiconductor device includes a source line, a bit line, a first signal line, a second signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line, a second driver circuit electrically connected to the first signal line, a third driver circuit electrically connected to the second signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

Abstract translation: 半导体器件包括源极线，位线，第一信号线，第二信号线，字线，在源极线和位线之间并联连接的存储器单元;第一驱动器电路，电连接到源极线 位线，电连接到第一信号线的第二驱动电路，与第二信号线电连接的第三驱动电路，以及电连接到字线的第四驱动电路。 存储单元包括第一晶体管，包括第一栅电极，第一源电极和第一漏电极，第二晶体管包括第二栅电极，第二源电极和第二漏极，以及电容器。 第二晶体管包括氧化物半导体材料。