公开(公告)号：US10461089B2

公开(公告)日：2019-10-29

申请号：US16167879

申请日：2018-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

IPC: H01L27/11521 ,  H01L21/762 ,  H01L27/11526 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11534 ,  H01L27/11548 ,  H01L23/528

Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

公开(公告)号：US20180151579A1

公开(公告)日：2018-05-31

申请号：US15694098

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

IPC: H01L27/11521 ,  H01L27/11526 ,  H01L21/762 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/762 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11548 ,  H01L29/42328

Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

公开(公告)号：US20180090631A1

公开(公告)日：2018-03-29

申请号：US15273880

申请日：2016-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Lee-Chuan Tseng ,  Ming Chyi Liu ,  Po-Chun Liu

IPC: H01L31/0352 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/02 ,  H01L31/103 ,  H01L31/105 ,  H01L31/18

CPC classification number: H01L31/035281 ,  H01L31/02005 ,  H01L31/02019 ,  H01L31/02161 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/1037 ,  H01L31/105 ,  H01L31/1808 ,  H01L31/1812

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. A dielectric layer is arranged over an upper surface of the silicon substrate, and extends over outer edges of the well region and includes an opening that leaves an inner portion of the well region exposed. An epitaxial pillar of SiGe or Ge extends upward from the inner portion of the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric sidewall structure surrounds the epitaxial pillar and has a bottom surface that rests on an upper surface of the dielectric layer.

公开(公告)号：US09768220B2

公开(公告)日：2017-09-19

申请号：US14253025

申请日：2014-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Yu-Hsing Chang ,  Ming Chyi Liu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L27/146 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/14638 ,  H01L21/76232 ,  H01L27/14607 ,  H01L27/14616 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14689 ,  H01L27/14692 ,  H01L29/0649

Abstract: Some embodiments of the present disclosure relate to a deep trench isolation structure. This deep trench isolation structure is formed on a semiconductor substrate having an upper semiconductor surface. A deep trench, which has a deep trench width as measured between opposing deep trench sidewalls, extends into the semiconductor substrate beneath the upper semiconductor surface. A fill material is formed in the deep trench, and a dielectric liner is disposed on a lower surface and sidewalls of the deep trench to separate the fill material from the semiconductor substrate. A shallow trench region has sidewalls that extend upwardly from the sidewalls of the deep trench to the upper semiconductor surface. The shallow trench region has a shallow trench width that is greater than the deep trench width. A dielectric material fills the shallow trench region and extends over top of the conductive material in the deep trench.

公开(公告)号：US09570454B2

公开(公告)日：2017-02-14

申请号：US14749970

申请日：2015-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Yu-Hsing Chang ,  Yuan-Tai Tseng

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L27/11524 ,  H01L27/11534 ,  H01L29/1037 ,  H01L29/42328 ,  H01L29/7851

Abstract: The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device.

Abstract translation: 本公开涉及具有FinFET器件和嵌入式闪存器件的集成芯片及其形成方法。 在一些实施例中，集成芯片具有与逻辑区域横向分离的逻辑区域和存储区域。 逻辑区域具有从半导体衬底向外突出的半导体材料的第一多个翅片。 栅电极设置在半导体材料的第一多个散热片上。 存储区域具有从半导体衬底向外延伸的第二多个半导体材料翅片。 嵌入式闪存单元被布置在半导体材料的第二多个鳍上。 所得到的集成芯片结构提供了良好的性能，因为它包含FinFET器件和嵌入式闪存器件。

公开(公告)号：US20160379987A1

公开(公告)日：2016-12-29

申请号：US14749970

申请日：2015-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Yu-Hsing Chang ,  Yuan-Tai Tseng

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/11524 ,  H01L27/11534 ,  H01L29/1037 ,  H01L29/42328 ,  H01L29/7851

Abstract: The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device.

Abstract translation: 本公开涉及具有FinFET器件和嵌入式闪存器件的集成芯片及其形成方法。 在一些实施例中，集成芯片具有与逻辑区域横向分离的逻辑区域和存储区域。 逻辑区域具有从半导体衬底向外突出的半导体材料的第一多个翅片。 栅电极设置在半导体材料的第一多个散热片上。 存储区域具有从半导体衬底向外延伸的第二多个半导体材料翅片。 嵌入式闪存单元被布置在半导体材料的第二多个鳍上。 所得到的集成芯片结构提供了良好的性能，因为它包含FinFET器件和嵌入式闪存器件。

公开(公告)号：US09349741B2

公开(公告)日：2016-05-24

申请号：US14330140

申请日：2014-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11524 ,  H01L21/28008 ,  H01L21/28273 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region. A logic device is arranged over the logic region and includes a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9. A flash memory cell device is arranged over the memory region. The flash memory cell device includes a memory cell gate electrically insulated on opposing sides by corresponding dielectric regions. A silicide contact pad is arranged over a top surface of the memory cell gate. The top surface of the memory cell gate and a top surface of the silicide contact pad are recessed relative to a top surface of the metal gate and top surfaces of the dielectric regions. A method of manufacturing the integrated circuit is also provided.

Abstract translation: 提供了一种用于嵌入式闪存设备的集成电路。 半导体衬底包括存储区域和与存储区域相邻的逻辑区域。 逻辑器件布置在逻辑区域上，并且包括通过具有超过3.9的介电常数的材料与半导体衬底分离的金属栅极。 闪存单元设备布置在存储器区域的上方。 闪存单元器件包括通过相应的电介质区域在相对侧上电绝缘的存储单元栅极。 硅化物接触焊盘设置在存储单元栅极的顶表面上方。 存储单元栅极的顶表面和硅化物接触焊盘的顶表面相对于金属栅极的顶表面和电介质区域的顶表面凹陷。 还提供了一种制造集成电路的方法。

公开(公告)号：US20150255718A1

公开(公告)日：2015-09-10

申请号：US14196361

申请日：2014-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00

CPC classification number: H01L45/1691 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

Abstract translation: 本公开涉及一种电阻随机存取存储器（RRAM）器件架构，其包括在RRAM单元的下部金属互连和底部电极之间的导电蚀刻停止层的薄单层。 导电蚀刻停止层提供了结构的简单性，并且该层的蚀刻选择性为下层提供了保护。 可以使用干式或湿式蚀刻来蚀刻导电蚀刻停止层以落在下部金属互连上。 在下金属互连是铜的情况下，蚀刻导电蚀刻停止层以露出铜不会像传统方法那样产生尽可能多的非挥发性铜蚀刻副产物。 与传统方法相比，所公开的技术的一些实施例减少了掩模步骤的数量，并且还减少了在形成底部电极期间的化学机械抛光。

公开(公告)号：US12159886B2

公开(公告)日：2024-12-03

申请号：US17361785

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Hung-Shu Huang

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to an image sensor, including a semiconductor substrate, a plurality of photodiodes disposed within the semiconductor substrate, and a deep trench isolation structure separating the plurality of photodiodes from one another and defining a plurality of pixel regions corresponding to the plurality of photodiodes. The plurality of pixel regions includes a first pixel region sensitive to a first region of a light spectrum, a second pixel region sensitive to a second region of the light spectrum, and a third pixel region sensitive to a third region of the light spectrum. The first pixel region is smaller than the second pixel region or the third pixel region.

公开(公告)号：US11990433B2

公开(公告)日：2024-05-21

申请号：US17366556

申请日：2021-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/49822 ,  H01L23/49844 ,  H01L24/03 ,  H01L25/0657 ,  H01L2224/03001 ,  H01L2224/033 ,  H01L2224/05556 ,  H01L2224/05573

Abstract: In some embodiments, the present disclosure relates to a device that includes an interconnect structure arranged on a frontside of a substrate. The interconnect structure includes interconnect conductive structures embedded within interconnect dielectric layers. A trench extends completely through the substrate to expose multiples ones of the interconnect conductive structures. A bond pad structure is arranged on a backside of the substrate and extends through the trench of the substrate to contact the multiple ones of the interconnect conductive structures. A bonding structure is arranged on the backside of the substrate and electrically contacts the bond pad structure.